Datasheet

PCAL6416A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 9 October 2014 12 of 61
NXP Semiconductors
PCAL6416A
Low-voltage translating 16-bit I
2
C-bus/SMBus I/O expander
7.4.3 Polarity inversion register pair (04h, 05h)
The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined
as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the
corresponding port pin’s polarity is inverted in the input register. If a bit in this register is
cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A register pair
write operation is described in Section 8.1
. A register pair read operation is described in
Section 8.2
.
7.4.4 Configuration register pair (06h, 07h)
The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a
bit in these registers is set to 1, the corresponding port pin is enabled as a
high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin
is enabled as an output. A register pair write operation is described in Section 8.1
. A
register pair read operation is described in Section 8.2
.
Table 11. Polarity inversion port 0 register (address 04h)
Bit 7 6 5 4 3 2 1 0
Symbol N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0
Default 00000000
Table 12. Polarity inversion port 1 register (address 05h)
Bit 7 6 5 4 3 2 1 0
Symbol N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0
Default 00000000
Table 13. Configuration port 0 register (address 06h)
Bit 7 6 5 4 3 2 1 0
Symbol C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0
Default 11111111
Table 14. Configuration port 1 register (address 07h)
Bit 7 6 5 4 3 2 1 0
Symbol C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0
Default 11111111