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1. General description

The PCAL6416A is a 16-bit general-purpose I/O expander that provides remote I/O

expansion for most microcontroller families via the I

C-bus interface.

NXP I/O expanders provide a simple solution when additional I/Os are needed while

keeping interconnections to a minimum, for example, in battery-powered mobile

applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing

a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage

level to I/O devices operating at a different (usually higher) voltage level. The PCAL6416A

has built-in level shifting feature that makes these devices extremely flexible in mixed

signal environments where communication between incompatible I/O voltages is required.

Its wide V

range of 1.65 V to 5.5 V on the dual power rail allows seamless

communications with next-generation low voltage microprocessors and microcontrollers

on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side.

There are two supply voltages for PCAL6416A: V

DD(I2C-bus)

and V

DD(P)

. V

DD(I2C-bus)

provides the supply voltage for the interface at the master side (for example, a

microcontroller) and the V

DD(P)

provides the supply for core circuits and Port P. The

bidirectional voltage level translation in the PCAL6416A is provided through V

DD(I2C-bus)

should be connected to the V

of the external SCL/SDA lines. This indicates

the V

level of the I

C-bus to the PCAL6416A, while the voltage level on Port P of the

PCAL6416A is determined by the V

DD(P)

The PCAL6416A contains the PCA6416A register set of four pairs of 8-bit Configuration,

Input, Output, and Polarity Inversion registers and additionally, the PCAL6416A has

Agile I/O, which are additional features specifically designed to enhance the I/O. These

additional features are: programmable output drive strength, latchable inputs,

programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register,

programmable open-drain or push-pull outputs. The PCAL6416A is a pin-to-pin

replacement to the PCA6416A, however, the PCAL6416A powers up with all I/O interrupts

masked. This mask default allows for a board bring-up free of spurious interrupts at

power-up.

At power-on, the I/Os are configured as inputs. However, the system master can enable

the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for

each input or output is kept in the corresponding input or output register. The polarity of

the Input Port register can be inverted with the Polarity Inversion register, saving external

logic gates. Programmable pull-up and pull-down resistors eliminate the need for discrete

components.

PCAL6416A

Low-voltage translating 16-bit I

C-bus/SMBus I/O expander

with interrupt output, reset, and configuration registers

Rev. 6 — 9 October 2014 Product data sheet

Summary of content (61 pages)

PAGE 1
PCAL6416A Low-voltage translating 16-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers Rev. 6 — 9 October 2014 Product data sheet 1. General description The PCAL6416A is a 16-bit general-purpose I/O expander that provides remote I/O expansion for most microcontroller families via the I2C-bus interface.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander The system master can reset the PCAL6416A in the event of a time-out or other improper operation by asserting a LOW in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander  Latched outputs with 25 mA drive maximum capability for directly driving LEDs  Latch-up performance exceeds 100 mA per JESD 78, Class II  ESD protection exceeds JESD 22  2000 V Human-Body Model (A114-A)  1000 V Charged-Device Model (C101)  Packages offered: TSSOP24, HWQFN24, UFBGA24, VFBGA24, XFBGA24 2.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 3.1 Ordering options Table 2.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 5. Pinning information 21 VDD(P) 23 VDD(I2C-bus) 24 RESET 5.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander ball A1 index area ball A1 index area PCAL6416AEX 1 2 3 4 PCAL6416AER 5 1 A A B B C C D D E E 2 002aah190 UFBGA24 with 0.24 mm ball size. Pin configuration for XFBGA24 (2 mm  2 mm); EX option A 5 Transparent top view XFBGA24 with 0.175 mm ball size. 1 4 aaa-009837 Transparent top view Fig 6. 3 2 Fig 7.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 5.2 Pin description Table 3. Symbol Pin description Pin Description TSSOP24 HWQFN24 VFBGA24 UFBGA24, XFBGA24 INT 1 22 A3 B3 Interrupt output. Connect to VDD(I2C-bus) or VDD(P) through a pull-up resistor. VDD(I2C-bus) 2 23 B3 A2 Supply voltage of I2C-bus. Connect directly to the VDD of the external I2C master. Provides voltage-level translation. RESET 3 24 A2 A1 Active LOW reset input.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 6. Voltage translation Table 4 shows how to set up VDD levels for the necessary voltage translation between the I2C-bus and the PCAL6416A. Table 4. PCAL6416A Product data sheet Voltage translation VDD(I2C-bus) (SDA and SCL of I2C master) VDD(P) (Port P) 1.8 V 1.8 V 1.8 V 2.5 V 1.8 V 3.3 V 1.8 V 5V 2.5 V 1.8 V 2.5 V 2.5 V 2.5 V 3.3 V 2.5 V 5V 3.3 V 1.8 V 3.3 V 2.5 V 3.3 V 3.3 V 3.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 7. Functional description Refer to Figure 1 “Block diagram of PCAL6416A (positive logic)”. 7.1 Device address The address of the PCAL6416A is shown in Figure 9. slave address 0 1 0 0 0 0 fixed AD R/W DR hardware selectable 002aah045 Fig 9. PCAL6416A address ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW (logic 0) to assign one of the two possible slave addresses.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander Table 6.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 7.4 Register descriptions 7.4.1 Input port register pair (00h, 01h) The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port registers are read only; writes to these registers have no effect. The default value ‘X’ is determined by the externally applied logic level.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 7.4.3 Polarity inversion register pair (04h, 05h) The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the corresponding port pin’s polarity is inverted in the input register. If a bit in this register is cleared (written with a ‘0’), the corresponding port pin’s polarity is retained.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 7.4.5 Output drive strength register pairs (40h, 41h, 42h, 43h) The Output drive strength registers control the output drive level of the GPIO. Each GPIO can be configured independently to a certain output current level by two register control bits. For example Port 0.7 is controlled by register 41 CC0.7 (bits [7:6]), Port 0.6 is controlled by register 41 CC0.6 (bits [5:4]).
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander cleared, assuming there were no additional input(s) that have changed, and bit 4 of the input port 0 register will read ‘1’. The next read of the input port register bit 4 register should now read ‘0’. An interrupt remains active when a non-latched input simultaneously switches state with a latched input and then returns to its original state.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 7.4.8 Pull-up/pull-down selection register pair (48h, 49h) The I/O port can be configured to have pull-up or pull-down resistor by programming the pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that I/O pin.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 7.4.10 Interrupt status register pair (4Ch, 4Dh) These read-only registers are used to identify the source of an interrupt. When read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin is not the source of an interrupt. When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit will return logic 0.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander data from shift register output port register data configuration register data from shift register D write configuration pulse CK VDD(P) Q Q1 ESD protection diode Q2 ESD protection diode FF D Q Q FF write pulse CK P0_0 to P0_7 P1_0 to P1_7 output port register VSS D Q input port register data FF read pulse CK VDD(P) PULL-UP/PULL-DOWN CONTROL INTERRUPT MASK input port register 100 kΩ D inp
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 7.8 Interrupt output (INT) An interrupt is generated by any rising or falling edge of the port inputs in the Input mode. After time tv(INT), the signal INT is valid. The interrupt is reset when data on the port changes back to the original value or when data is read from the port that generated the interrupt (see Figure 17).
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 8.2 Read commands To read data from the PCAL6416A, the bus master must first send the PCAL6416A address with the least significant bit set to a logic 0 (see Figure 9 for device address). The command byte is sent after the address and determines which register is to be accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1.
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PAGE 23
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 9. Application design-in information VDD(I2C-bus) VDD(P) 10 kΩ (×7) VDD(I2C-bus) = 1.8 V 10 kΩ VDD 10 kΩ 10 kΩ SUBSYSTEM 1 (e.g.
PAGE 25
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 3.3 V VDD VDD(P) LED 5V VDD(P) 100 kΩ LED Pn Pn 002aah278 Fig 19. High value resistor in parallel with the LED 002aah279 Fig 20. Device supplied by a lower voltage 9.2 Output drive strength control The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can be configured independently to one of the four possible output current levels.
PAGE 26
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander Reducing the current drive capability may be desirable to reduce system noise. When the output switches (transitions from H/L), there is a peak current that is a function of the output drive selection. This peak current runs through VDD and VSS package inductance and will create noise (some radiated, but more critically Simultaneous Switching Noise (SSN)).
PAGE 27
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander Table 30. Recommended supply sequencing and ramp rates Tamb = 25 C (unless otherwise noted). Not tested; specified by design. Symbol Parameter Condition Min Typ Max Unit (dV/dt)f fall rate of change of voltage Figure 22 0.1 - 2000 ms (dV/dt)r rise rate of change of voltage Figure 22 0.1 - 2000 ms td(rst) reset delay time Figure 22; re-ramp time when VDD(P) drops below 0.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 9.4 Device current consumption with internal pull-up and pull-down resistors The PCAL6416A integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander more clocks ensures the slave state machine returns to a known, idle state since the protocol calls for eight data bits and one ACK bit. It does not matter when the slave state machine finishes its transmission, extra clocks will be recognized as STOP conditions. The PCAL6416A SCL pin is an input only.
PAGE 30
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 11. Recommended operating conditions Table 32. Operating conditions Symbol Parameter VDD(I2C-bus) I2C-bus VDD(P) supply voltage port P VIH HIGH-level input voltage Conditions supply voltage LOW-level input voltage VIL Min Max Unit 1.65 5.5 V 1.65 5.5 V SCL, SDA, RESET 0.7  VDD(I2C-bus) 5.5 V ADDR, P1_7 to P0_0 0.7  VDD(P) 5.5 V SCL, SDA, RESET 0.5 0.
PAGE 31
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 13. Static characteristics Table 34. Static characteristics Tamb = 40 C to +85 C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VIK input clamping voltage II = 18 mA 1.2 - - V VPOR power-on reset voltage VI = VDD(P) or VSS; IO = 0 mA - 1.1 1.4 V VOH HIGH-level output voltage[2] P port; IOH = 8 mA; CCX.X = 11b VDD(P) = 1.65 V 1.
PAGE 32
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander Table 34. Static characteristics …continued Tamb = 40 C to +85 C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified. Min Typ[1] Max Unit VDD(P) = 3.6 V to 5.5 V - 10 25 A VDD(P) = 2.3 V to 3.6 V - 6.5 15 A VDD(P) = 1.65 V to 2.3 V - 4 9 A VDD(P) = 3.6 V to 5.5 V - 1.5 7 A VDD(P) = 2.3 V to 3.6 V - 1 3.2 A VDD(P) = 1.65 V to 2.3 V - 0.5 1.
PAGE 33
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander [1] For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V, 3.6 V or 5 V VDD) and Tamb = 25 C. Except for IDD, the typical values are at VDD(P) = VDD(I2C-bus) = 3.3 V and Tamb = 25 C. [2] The total current sourced by all I/Os must be limited to 160 mA.
PAGE 34
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander Isink (mA) 002aaf578 35 Isink (mA) 30 Tamb = −40 °C 25 °C 85 °C 25 002aaf579 35 30 Tamb = −40 °C 25 °C 85 °C 25 20 20 15 15 10 10 5 5 0 0 0 0.1 0.2 0.3 0 0.1 0.2 VOL (V) a. VDD(P) = 1.65 V Isink (mA) b. VDD(P) = 1.8 V 002aaf580 50 002aaf581 60 Isink (mA) 40 Tamb = −40 °C 25 °C 85 °C 30 0.3 VOL (V) Tamb = −40 °C 25 °C 85 °C 40 20 20 10 0 0 0 0.1 0.2 0.3 0 0.1 0.2 VOL (V) c.
PAGE 35
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 002aaf561 30 Isource (mA) Isource (mA) Tamb = −40 °C 25 °C 85 °C 20 002aaf562 35 Tamb = −40 °C 25 °C 85 °C 30 25 20 15 10 10 5 0 0 0 0.2 0.4 0.6 VDD(P) − VOH (V) a. VDD(P) = 1.65 V 0 002aaf563 Isource (mA) Tamb = −40 °C 25 °C 85 °C 40 0.4 0.6 VDD(P) − VOH (V) b. VDD(P) = 1.8 V 60 Isource (mA) 0.2 002aaf564 70 Tamb = −40 °C 25 °C 85 °C 60 50 40 30 20 20 10 0 0 0 0.2 0.4 0.
PAGE 36
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander VOL (mV) 002aah056 120 100 002aah057 200 VDD(P) − VOH (mV) 160 (1) 80 120 VDD(P) = 1.8 V 5V 60 (2) 80 40 (4) 20 0 −40 40 (3) −15 10 35 60 85 Tamb (°C) 0 −40 −15 10 35 60 85 Tamb (°C) Isource = 10 mA (1) VDD(P) = 1.8 V; Isink = 10 mA (2) VDD(P) = 5 V; Isink = 10 mA (3) VDD(P) = 1.8 V; Isink = 1 mA (4) VDD(P) = 5 V; Isink = 1 mA Fig 32. LOW-level output voltage versus temperature with CCX.
PAGE 37
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 14. Dynamic characteristics Table 35. I2C-bus interface timing requirements Over recommended operating free air temperature range, unless otherwise specified. See Figure 35. Symbol Parameter Conditions Standard-mode I2C-bus Fast-mode I2C-bus Unit Min Max Min Max fSCL SCL clock frequency 0 100 0 400 tHIGH HIGH period of the SCL clock 4 - 0.6 - s tLOW LOW period of the SCL clock 4.7 - 1.
PAGE 38
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander Table 37. Switching characteristics Over recommended operating free air temperature range; CL  100 pF; unless otherwise specified. See Figure 36.
PAGE 39
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander VDD(I2C-bus) RL = 4.7 kΩ INT DUT CL = 100 pF 002aag979 a.
PAGE 40
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 500 Ω Pn DUT 2 × VDD(P) CL = 50 pF 500 Ω 002aag981 a. P port load configuration SCL P0 A P7 0.7 × VDD(I2C-bus) 0.3 × VDD(I2C-bus) SDA tv(Q) Pn unstable data last stable bit A P7 002aag982 b. Write mode (R/W = 0) SCL P0 0.7 × VDD(I2C-bus) 0.3 × VDD(I2C-bus) tsu(D) th(D) Pn 0.5 × VDD(P) 002aag983 c. Read mode (R/W = 1) CL includes probe and jig capacitance. tv(Q) is measured from 0.
PAGE 41
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander VDD(I2C-bus) RL = 1 kΩ SDA DUT 500 Ω Pn DUT CL = 50 pF 2 × VDD(P) CL = 50 pF 500 Ω 002aag977 002aag981 a. SDA load configuration b. P port load configuration START SCL ACK or read cycle SDA 0.3 × VDD(I2C-bus) trst RESET 0.5 × VDD(I2C-bus) trec(rst) tw(rst) trec(rst) trst Pn 0.5 × VDD(P) 002aag984 c. RESET timing CL includes probe and jig capacitance.
PAGE 42
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 16.
PAGE 43
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PAGE 47
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
PAGE 48
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 17.
PAGE 49
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 43. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”.
PAGE 50
PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 18.
PAGE 51
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 19. Abbreviations Table 40. Abbreviations Acronym Description ESD ElectroStatic Discharge FET Field-Effect Transistor GPIO General Purpose Input/Output I2C-bus Inter-Integrated Circuit bus I/O Input/Output LED Light-Emitting Diode LSB Least Significant Bit MSB Most Significant Bit PCB Printed-Circuit Board POR Power-On Reset SMBus System Management Bus 20. Revision history Table 41.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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PCAL6416A NXP Semiconductors Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 23. Contents 1 2 2.1 3 3.1 4 5 5.1 5.2 6 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.11 7.5 7.6 7.7 7.8 8 8.1 8.2 9 9.1 9.2 9.3 9.4 9.5 10 11 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 Agile I/O features . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . .