Datasheet

PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 18 September 2013 8 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
7.2 Interface definition
7.3 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCAL6408A. 2 bits of this
data byte state the operation (read or write) and the internal registers (Input, Output,
Polarity Inversion, or Configuration) that are affected. Bit 6 in conjunction with the lower
3 bits of the Command byte are used to point to the extended features of the device
(Agile I/O). This register is ‘write only’.
[1] Undefined.
Table 5. Interface definition
Byte Bit
7 (MSB) 6 5 4 3 2 1 0 (LSB)
I
2
C-bus slave address L H L L L L ADDR R/W
I/O data bus P7 P6 P5 P4 P3 P2 P1 P0
Fig 8. Pointer register bits
002aaf540
B7 B6 B5 B4 B3 B2 B1 B0
Table 6. Command byte
Pointer register bits Command byte Register Protocol Power-up
default
B7 B6 B5 B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 00h Input port read byte xxxx xxxx
[1]
0 0 0 0 0 0 0 1 01h Output port read/write byte 1111 1111
0 0 0 0 0 0 1 0 02h Polarity Inversion read/write byte 0000 0000
0 0 0 0 0 0 1 1 03h Configuration read/write byte 1111 1111
0 1 0 0 0 0 0 0 40h Output drive strength 0 read/write byte 1111 1111
0 1 0 0 0 0 0 1 41h Output drive strength 1 read/write byte 1111 1111
0 1 0 0 0 0 1 0 42h Input latch read/write byte 0000 0000
0 1 0 0 0 0 1 1 43h Pull-up/pull-down enable read/write byte 0000 0000
0 1 0 0 0 1 0 0 44h Pull-up/pull-down selection read/write byte 1111 1111
0 1 0 0 0 1 0 1 45h Interrupt mask read/write byte 1111 1111
0 1 0 0 0 1 1 0 46h Interrupt status read byte 0000 0000
0 1 0 0 1 1 1 1 4Fh Output port configuration read/write byte 0000 0000