Datasheet

PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 18 September 2013 6 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
5.2 Pin description
[1] All I/O are configured as input at power-on.
Fig 5. Pin configuration for
1.6 mm  1.6 mm XFBGA16
Fig 6. Ball mapping for
1.6 mm  1.6 mm XFBGA16
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Table 3. Pin description
Symbol Pin Description
TSSOP16 HVQFN16 XQFN16 XFBGA16
V
DD(I2C-bus)
1 15 15 A2 Supply voltage of I
2
C-bus. Connect directly to the V
DD
of
the external I
2
C master. Provides voltage-level
translation.
ADDR 2 16 16 B2 Address input. Connect directly to V
DD(P)
or ground.
RESET
3 1 1 A1 Active LOW reset input. Connect to V
DD(I2C-bus)
through a
pull-up resistor if no active connection is used.
P0
[1]
4 2 2 B1 Port P input/output 0.
P1
[1]
5 3 3 C2 Port P input/output 1.
P2
[1]
6 4 4 C1 Port P input/output 2.
P3
[1]
7 5 5 D1 Port P input/output 3.
V
SS
8 6 6 D2 Ground.
P4
[1]
9 7 7 D3 Port P input/output 4.
P5
[1]
10 8 8 D5 Port P input/output 5.
P6
[1]
11 9 9 C4 Port P input/output 6.
P7
[1]
12 10 10 C3 Port P input/output 7.
INT
13 11 11 B4 Interrupt output. Connect to V
DD(I2C-bus)
through a pull-up
resistor.
SCL 14 12 12 A4 Serial clock bus. Connect to V
DD(I2C-bus)
through a pull-up
resistor.
SDA 15 13 13 B3 Serial data bus. Connect to V
DD(I2C-bus)
through a pull-up
resistor.
V
DD(P)
16 14 14 A3 Supply voltage of PCAL6408A for Port P.