Datasheet
PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 18 September 2013 31 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
14. Dynamic characteristics
Table 24. I
2
C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 31.
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Unit
Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
HIGH
HIGH period of the SCL clock 4 - 0.6 - s
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - s
t
SP
pulse width of spikes that must
be suppressed by the input filter
0 50 0 50 ns
t
SU;DAT
data set-up time 250 - 100 - ns
t
HD;DAT
data hold time 0 - 0 - ns
t
r
rise time of both SDA and SCL signals - 1000 20 300 ns
t
f
fall time of both SDA and SCL signals - 300 20
(V
DD
/5.5V)
300 ns
t
BUF
bus free time between a STOP and
START condition
4.7 - 1.3 - s
t
SU;STA
set-up time for a repeated START
condition
4.7 - 0.6 - s
t
HD;STA
hold time (repeated) START condition 4 - 0.6 - s
t
SU;STO
set-up time for STOP condition 4 - 0.6 - s
t
VD;DAT
data valid time SCL LOW to
SDA output valid
-3.45 - 0.9s
t
VD;ACK
data valid acknowledge time ACK signal from
SCL LOW to
SDA (out) LOW
-3.45 - 0.9s
Table 25. Reset timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 34
.
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode
I
2
C-bus
Unit
Min Max Min Max
t
w(rst)
reset pulse width 30 - 30 - ns
t
rec(rst)
reset recovery time 200 - 200 - ns
t
rst
reset time 600 - 600 - ns