Datasheet
PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 18 September 2013 26 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
[1] All typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V or 5 V V
DD
) and T
amb
=25C.
[2] When power (from 0 V) is applied to V
DD(P)
, an internal power-on reset holds the PCAL6408A in a reset condition until V
DD(P)
has
reached V
POR
. At that time, the reset condition is released, and the PCAL6408A registers and I
2
C-bus/SMBus state machine initialize to
their default states. After that, V
DD(P)
must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle.
[3] The total current sourced by all I/Os must be limited to 80 mA.
[4] Each I/O must be externally limited to a maximum of 25 mA, for a device total of 200 mA.
[5] Typical value for T
amb
=25C. V
OL
= 0.4 V and V
DD
= 3.3 V. Typical value for V
DD
<2.5V, V
OL
=0.6V.
[6] Internal pull-up/pull-down resistor disabled.
I
DD
additional quiescent
supply current
[6]
SCL, SDA, RESET;
one input at V
DD(I2C-bus)
0.6 V,
other inputs at V
DD(I2C-bus)
or V
SS
;
V
DD(P)
= 1.65 V to 5.5 V
--25A
P port, ADDR;
one input at V
DD(P)
0.6 V,
other inputs at V
DD(P)
or V
SS
;
V
DD(P)
= 1.65 V to 5.5 V
--80A
C
i
input capacitance SCL; V
I
=V
DD(I2C-bus)
or V
SS
;
V
DD(P)
= 1.65 V to 5.5 V
-67pF
C
io
input/output capacitance SDA; V
I/O
=V
DD(I2C-bus)
or V
SS
;
V
DD(P)
= 1.65 V to 5.5 V
-78pF
P port; V
I/O
=V
DD(P)
or V
SS
;
V
DD(P)
= 1.65 V to 5.5 V
-7.58.5pF
R
pu(int)
internal pull-up resistance input/output 50 100 150 k
R
pd(int)
internal pull-down
resistance
input/output 50 100 150 k
Table 23. Static characteristics …continued
T
amb
=
40
C to +85
C; V
DD(I2C-bus)
= 1.65 V to 5.5 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit