Datasheet

PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 18 September 2013 2 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
The system master can reset the PCAL6408A in the event of a time-out or other improper
operation by asserting a LOW in the RESET
input. The power-on reset puts the registers
in their default state and initializes the I
2
C-bus/SMBus state machine. The RESET pin
causes the same reset/initialization to occur without de-powering the part.
The PCAL6408A open-drain interrupt (INT
) output is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed.
INT
can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I
2
C-bus. Thus, the PCAL6408A can
remain a simple slave device. The input latch feature holds or latches the input pin state
and keeps the logic values that created the interrupt until the master can service the
interrupt. This minimizes the host’s interrupt service response for fast moving inputs.
The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while
consuming low device current.
One hardware pin (ADDR) can be used to program and vary the fixed I
2
C-bus address
and allow up to two devices to share the same I
2
C-bus or SMBus.
2. Features and benefits
 I
2
C-bus to parallel port expander
 Operating power supply voltage range of 1.65 V to 5.5 V
 Allows bidirectional voltage-level translation and GPIO expansion between:
 1.8V SCL/SDA and 1.8V, 2.5V, 3.3V or 5V PortP
 2.5V SCL/SDA and 1.8V, 2.5V, 3.3V or 5V PortP
 3.3V SCL/SDA and 1.8V, 2.5V, 3.3V or 5V PortP
 5V SCL/SDA and 1.8V, 2.5V, 3.3V or 5V PortP
 Low standby current consumption of 1 A
 Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
 V
hys
= 0.18 V (typical) at 1.8 V
 V
hys
= 0.25 V (typical) at 2.5 V
 V
hys
= 0.33 V (typical) at 3.3 V
 V
hys
= 0.5 V (typical) at 5 V
 5 V tolerant I/O ports
 Active LOW reset input (RESET
)
 Open-drain active LOW interrupt output (INT
)
 400 kHz Fast-mode I
2
C-bus
 Internal power-on reset
 Power-up with all channels configured as inputs
 No glitch on power-up
 Noise filter on SCL/SDA inputs
 Latched outputs with 25 mA drive maximum capability for directly driving LEDs
 Latch-up performance exceeds 100 mA per JESD 78, Class II