Datasheet

PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 18 September 2013 17 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port
register).
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and
actual data transfer from P port (see Figure 12
).
Fig 14. Read Input port register (latch enabled)
10000
AD
DR
1 AS0
slave address
START condition R/W acknowledge from slave
002aah091
data from port
A
acknowledge from master
SDA 1
no acknowledge
from master
read from
port
data into
port
data from port
DATA 1
DATA 1
INT
DATA 2
DATA 2
P
STOP
condition
t
v(INT)
t
rst(INT)
t
h(D)
t
su(D)
12345678SCL 9
DATA 1
INT is cleared by
read from port
STOP not needed
to clear INT