Datasheet

PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 18 September 2013 15 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
8. Bus transactions
The PCAL6408A is an I
2
C-bus slave device. Data is exchanged between the master and
PCAL6408A through write and read commands using I
2
C-bus. The two communication
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Write commands
Data is transmitted to the PCAL6408A by sending the device address and setting the
Least Significant Bit (LSB) to a logic 0 (see Figure 7
for device address). The command
byte is sent after the address and determines which register receives the data that follows
the command byte. There is no limitation on the number of data bytes sent in one write
transmission.
Fig 10. Write to Output port register
0 AS
slave address
START condition R/W acknowledge
from slave
002aaf825
00000010
command byte
A
acknowledge
from slave
12345678SCL 9
SDA
DATA 1 A
write to port
data out from port
t
v(Q)
acknowledge
from slave
DATA 1 VALID
data to port
10000
AD
DR
0 P
STOP
condition
Fig 11. Write to Configuration or Polarity inversion registers
0 AS
slave address
START condition R/W acknowledge
from slave
002aah090
1/0 0 0 0 1/0 1/0 1/00
command byte
A
acknowledge
from slave
12345678SCL 9
SDA
DATA 1 A
acknowledge
from slave
data to register
10000
AD
DR
0 P
STOP
condition