Datasheet

PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 18 September 2013 14 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
7.6 Power-on reset
When power (from 0 V) is applied to V
DD(P)
, an internal power-on reset holds the
PCAL6408A in a reset condition until V
DD(P)
has reached V
POR
. At that time, the reset
condition is released and the PCAL6408A registers and I
2
C-bus/SMBus state machine
initialize to their default states. After that, V
DD(P)
must be lowered to below V
POR
and back
up to the operating voltage for a power-reset cycle. See Section 9.3 “
Power-on reset
requirements”.
7.7 Reset input (RESET)
The RESET input can be asserted to initialize the system while keeping the V
DD(P)
at its
operating level. A reset can be accomplished by holding the RESET
pin LOW for a
minimum of t
w(rst)
. The PCAL6408A registers and I
2
C-bus/SMBus state machine are
changed to their default state once RESET
is LOW (0). When RESET is HIGH (1), the I/O
levels at the P port can be changed externally or through the master. This input requires a
pull-up resistor to V
DD(I2C-bus)
if no active connection is used.
7.8 Interrupt output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time t
v(INT)
, the signal INT is valid. Resetting the interrupt circuit is achieved when
data on the port is changed to the original setting or when data is read from the port that
generated the interrupt (see Figure 13
). Resetting occurs in the Read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL
signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very
short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after
resetting is detected and is transmitted as INT
.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input port register.
The INT
output has an open-drain structure and requires a pull-up resistor to V
DD(P)
or
V
DD(I2C-bus)
depending on the application. INT should be connected to the voltage source
of the device that requires the interrupt information. When using the input latch feature,
the input pin state is latched. The interrupt is reset only when data is read from the port
that generated the interrupt. The reset occurs in the Read mode at the acknowledge
(ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.