Datasheet

PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 18 September 2013 10 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
7.4.5 Output drive strength registers (40h, 41h)
The Output drive strength registers control the output drive level of the GPIO. Each GPIO
can be configured independently to a certain output current level by two register control
bits. For example, Port 7 is controlled by register 41 CC7 (bits [7:6]), Port 6 is controlled
by register 41 CC6 (bits [5:4]). The output drive level of the GPIO is programmed
00b = 0.25, 01b = 0.5, 10b = 0.75 or 11b = 1 of the drive capability of the I/O.
See Section 9.2 “
Output drive strength control” for more details.
7.4.6 Input latch register (42h)
The Input latch register enables and disables the input latch of the I/O pins. These
registers are effective only when the pin is configured as an input port. When an input
latch register bit is 0, the corresponding input pin state is not latched. A state change in
the corresponding input pin generates an interrupt. A read of the input port register clears
the interrupt. If the input goes back to its initial logic state before the input port register is
read, then the interrupt is cleared. See Figure 13
.
When an input latch register bit is 1, the corresponding input pin state is latched. A change
of state of the input generates an interrupt and the input logic value is loaded into the
corresponding bit of the input port register (registers 0). A read of the input port register
clears the interrupt. If the input pin returns to its initial logic state before the input port
register is read, then the interrupt is not cleared and the corresponding bit of the input port
register keeps the logic value that initiated the interrupt. See Figure 14
. For example, if the
P4 input was as logic 0 and the input goes to logic 1 then back to logic 0, the input port
register captures this change and an interrupt is generated (if unmasked). When the read
is performed on the input port register, the interrupt is cleared, assuming there were no
additional input(s) that have changed, and bit 4 of the input port register reads ‘1’. The
next read of the input port register bit 4 should now read ‘0’.
An interrupt remains active when a non-latched input simultaneously switches state with a
latched input and then returns to its original state. A read of the input port register reflects
only the change of state of the latched input and also clears the interrupt. The interrupt is
not cleared if the input latch register changes from latched to non-latched configuration.
If the input pin is changed from latched to non-latched input, a read from the input port
register reflects the current port logic level. If the input pin is changed from non-latched to
latched input, the read from the input port register reflects the latched logic level.
Table 11. Current control register (address 40h)
Bit 7 6 5 4 3 2 1 0
Symbol CC3 CC2 CC1 CC0
Default 11111111
Table 12. Current control register (address 41h)
Bit 7 6 5 4 3 2 1 0
Symbol CC7 CC6 CC5 CC4
Default 11111111