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1. General description

The PCAL6408A is an 8-bit general-purpose I/O expander that provides remote I/O

expansion for most microcontroller families via the I

C-bus interface.

NXP I/O expanders provide a simple solution when additional I/Os are needed while

keeping interconnections to a minimum, for example, in battery-powered mobile

applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing

a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage

level to I/O devices operating at a different (usually higher) voltage level. The PCAL6408A

has built-in level shifting feature that makes these devices extremely flexible in mixed

signal environments where communication between incompatible I/O voltages is required.

Its wide V

range of 1.65 V to 5.5 V on the dual power rail allows seamless

communications with next-generation low voltage microprocessors and microcontrollers

on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side.

There are two supply voltages for PCAL6408A: V

DD(I2C-bus)

and V

DD(P)

. V

DD(I2C-bus)

provides the supply voltage for the interface at the master side (for example, a

microcontroller) and the V

DD(P)

provides the supply for core circuits and Port P. The

bidirectional voltage level translation in the PCAL6408A is provided through V

DD(I2C-bus)

should be connected to the V

of the external SCL/SDA lines. This indicates

the V

level of the I

C-bus to the PCAL6408A, while the voltage level on Port P of the

PCAL6408A is determined by the V

DD(P)

The PCAL6408A contains the PCA6408A register set of 8-bit Configuration, Input, Output,

and Polarity Inversion registers and additionally, the PCAL6408A has Agile I/O, which are

additional features specifically designed to enhance the I/O. These additional features

are: programmable output drive strength, latchable inputs, programmable

pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable

open-drain or push-pull outputs. The PCAL6408A is a pin-to-pin replacement to the

PCA6408A, however, the PCAL6408A powers up with all I/O interrupts masked. This

mask default allows for a board bring-up free of spurious interrupts at power-up.

At power-on, the I/Os are configured as inputs. However, the system master can enable

the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for

each input or output is kept in the corresponding input or output register. The polarity of

the Input Port register can be inverted with the Polarity Inversion register, saving external

logic gates. Programmable pull-up and pull-down resistors eliminate the need for discrete

components.

PCAL6408A

Low-voltage translating, 8-bit I

C-bus/SMBus I/O expander

with interrupt output, reset, and configuration registers

Rev. 3 — 18 September 2013 Product data sheet

Summary of content (49 pages)

PAGE 1
PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers Rev. 3 — 18 September 2013 Product data sheet 1. General description The PCAL6408A is an 8-bit general-purpose I/O expander that provides remote I/O expansion for most microcontroller families via the I2C-bus interface.
PAGE 2
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander The system master can reset the PCAL6408A in the event of a time-out or other improper operation by asserting a LOW in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander  ESD protection exceeds JESD 22  2000 V Human-Body Model (A114-A)  1000 V Charged-Device Model (C101)  Packages offered: HVQFN16, TSSOP16, XQFN16, XFBGA16 (1.6 mm  1.6 mm  0.5 mm) 2.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 3.1 Ordering options Table 2.
PAGE 5
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 5. Pinning information 13 SDA 2 15 SDA P0 3 14 SCL P1 3 10 P7 P0 4 13 INT P1 5 P2 4 9 P2 6 11 P6 8 P3 7 10 P5 P5 11 INT ADDR RESET 7 2 12 SCL P4 1 6 RESET VSS 8 VSS 16 VDD(P) 5 1 P3 VDD(I2C-bus) 14 VDD(P) terminal 1 index area 15 VDD(I2C-bus) 16 ADDR 5.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 3&$/ $(; EDOO $ LQGH[ DUHD $ % & ' $ 5(6(7 9'' , & EXV 9'' 3 6&/ % 3 $''5 6'$ ,17 & 3 3 3 3 ' 3 966 3 DDK 7UDQVSDUHQW WRS YLHZ 7UDQVSDUHQW WRS YLHZ Fig 5. 3 DDK Pin configuration for 1.6 mm  1.6 mm XFBGA16 Fig 6. Ball mapping for 1.6 mm  1.6 mm XFBGA16 5.2 Pin description Table 3.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 6. Voltage translation Table 4 shows how to set up VDD levels for the necessary voltage translation between the I2C-bus and the PCAL6408A. Table 4. Voltage translation VDD(I2C-bus) (SDA and SCL of I2C master) VDD(P) (Port P) 1.8 V 1.8 V 1.8 V 2.5 V 1.8 V 3.3 V 1.8 V 5V 2.5 V 1.8 V 2.5 V 2.5 V 2.5 V 3.3 V 2.5 V 5V 3.3 V 1.8 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 5V 5V 1.8 V 5V 2.5 V 5V 3.
PAGE 8
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 7.2 Interface definition Table 5. Interface definition Byte I2C-bus Bit slave address I/O data bus 7 (MSB) 6 5 4 3 2 1 0 (LSB) L H L L L L ADDR R/W P7 P6 P5 P4 P3 P2 P1 P0 7.3 Pointer register and command byte Following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the Pointer register in the PCAL6408A.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 7.4 Register descriptions 7.4.1 Input port register (00h) The Input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port register is read only; writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 7.4.5 Output drive strength registers (40h, 41h) The Output drive strength registers control the output drive level of the GPIO. Each GPIO can be configured independently to a certain output current level by two register control bits. For example, Port 7 is controlled by register 41 CC7 (bits [7:6]), Port 6 is controlled by register 41 CC6 (bits [5:4]). The output drive level of the GPIO is programmed 00b = 0.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Table 13. Input latch register (address 42h) Bit 7 6 5 4 3 2 1 0 Symbol L7 L6 L5 L4 L3 L2 L1 L0 Default 0 0 0 0 0 0 0 0 7.4.7 Pull-up/pull-down enable register (43h) This register allows the user to enable or disable pull-up/pull-down resistors on the I/O pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 7.4.10 Interrupt status register (46h) This read-only register is used to identify the source of an interrupt. When read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin is not the source of an interrupt. When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit returns logic 0. Table 17.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 7.5 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output port register. In this case, there are low-impedance paths between the I/O pin and either VDD(P) or VSS.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 7.6 Power-on reset When power (from 0 V) is applied to VDD(P), an internal power-on reset holds the PCAL6408A in a reset condition until VDD(P) has reached VPOR. At that time, the reset condition is released and the PCAL6408A registers and I2C-bus/SMBus state machine initialize to their default states. After that, VDD(P) must be lowered to below VPOR and back up to the operating voltage for a power-reset cycle.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 8. Bus transactions The PCAL6408A is an I2C-bus slave device. Data is exchanged between the master and PCAL6408A through write and read commands using I2C-bus. The two communication lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device.
PAGE 16
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 8.2 Read commands To read data from the PCAL6408A, the bus master must first send the PCAL6408A address with the least significant bit set to a logic 0 (see Figure 7 for device address). The command byte is sent after the address and determines which register is to be accessed. After a restart the device address is sent again, but this time the LSB is set to a logic 1.
PAGE 17
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 0 1 0 0 START condition 0 data from port 0 AD 1 DR R/W DATA 1 A data from port A acknowledge from slave DATA 2 acknowledge from master read from port data into port DATA 1 tsu(D) INT tv(INT) 1 P STOP condition DATA 1 DATA 2 th(D) no acknowledge from master trst(INT) INT is cleared by read from port STOP not needed to clear INT 002aah091 Trans
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 9. Application design-in information VDD(I2C-bus) VDD(P) VDD(I2C-bus) = 1.8 V 10 kΩ 10 kΩ 10 kΩ 10 kΩ VDD 10 kΩ (× 3) VDD(I2C-bus) VDD(P) MASTER CONTROLLER SCL SDA P0 SCL SDA INT RESET SUBSYSTEM 1 (e.g., alarm system) A INT RESET VSS ALARM(1) P1 controlled switch enable B PCAL6408A P2 P3 ADDR P4 P5 KEYPAD P6 VSS P7 002aah092 Device address configured as 0100 000x for this example.
PAGE 19
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 3.3 V VDD VDD(P) LED 5V VDD(P) 100 kΩ LED Pn Pn 002aah278 Fig 16. High-value resistor in parallel with the LED 002aah279 Fig 17. Device supplied by a lower voltage 9.2 Output drive strength control The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can be configured independently to one of the four possible output current levels.
PAGE 20
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Reducing the current drive capability may be desirable to reduce system noise. When the output switches (transitions from H/L), there is a peak current that is a function of the output drive selection. This peak current runs through VDD and VSS package inductance and creates noise (some radiated, but more critically Simultaneous Switching Noise (SSN)).
PAGE 21
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Table 19. Recommended supply sequencing and ramp rates Tamb = 25 C (unless otherwise noted). Not tested; specified by design. Symbol Parameter Condition Min Typ Max Unit (dV/dt)f fall rate of change of voltage Figure 19 0.1 - 2000 ms (dV/dt)r rise rate of change of voltage Figure 19 0.1 - 2000 ms td(rst) reset delay time Figure 19; re-ramp time when VDD(P) drops below 0.
PAGE 22
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 9.4 Device current consumption with internal pull-up and pull-down resistors The PCAL6408A integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails.
PAGE 23
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 10. Limiting values Table 20. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD(I2C-bus) I2C-bus Conditions Min Max Unit 0.5 +6.5 V VDD(P) supply voltage port P VI input voltage [1] 0.5 +6.5 V 0.5 +6.5 VO output voltage [1] V 0.5 +6.
PAGE 24
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 12. Thermal characteristics Table 22. Symbol Zth(j-a) [1] Thermal characteristics Parameter Conditions transient thermal impedance from junction to ambient Max Unit TSSOP16 package [1] 108 K/W HVQFN16 package [1] 53 K/W XQFN16 package [1] 184 K/W The package thermal impedance is calculated in accordance with JESD 51-7. 13. Static characteristics Table 23.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Table 23. Static characteristics …continued Tamb = 40 C to +85 C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified. Symbol IOL Parameter LOW-level output current Min Typ[1] Max Unit 3 - - mA 3 15[5] - mA SCL, SDA, RESET; VI = VDD(I2C-bus) or VSS - - 1 A ADDR; VI = VDD(P) or VSS - - 1 A Conditions VOL = 0.4 V; VDD(P) = 1.65 V to 5.5 V SDA INT II input current [4] VDD(P) = 1.
PAGE 26
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Table 23. Static characteristics …continued Tamb = 40 C to +85 C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IDD additional quiescent supply current[6] SCL, SDA, RESET; one input at VDD(I2C-bus)  0.6 V, other inputs at VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V - - 25 A P port, ADDR; one input at VDD(P)  0.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 13.1 Typical characteristics 002aag973 20 IDD (μA) 002aag974 1400 IDD(stb) (nA) 16 VDD(P) = 5.5 V 5.0 V 3.6 V 12 3.3 V 2.5 V 2.3 V 8 VDD(P) = 5.5 V 5.0 V 3.6 V 3.3 V 1000 800 600 400 2.5 V 2.3 V 1.8 V 1.65 V 4 0 −40 200 VDD(P) = 1.8 V 1.65 V −15 10 35 60 85 Tamb (°C) Fig 23. Supply current versus ambient temperature 002aag975 20 IDD (μA) 16 0 −40 −15 10 35 60 85 Tamb (°C) Fig 24.
PAGE 28
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Isink (mA) 002aaf578 35 Isink (mA) 30 Tamb = −40 °C 25 °C 85 °C 25 002aaf579 35 30 Tamb = −40 °C 25 °C 85 °C 25 20 20 15 15 10 10 5 5 0 0 0 0.1 0.2 0.3 0 0.1 0.2 VOL (V) a. VDD(P) = 1.65 V Isink (mA) b. VDD(P) = 1.8 V 002aaf580 50 002aaf581 60 Isink (mA) 40 Tamb = −40 °C 25 °C 85 °C 30 0.3 VOL (V) Tamb = −40 °C 25 °C 85 °C 40 20 20 10 0 0 0 0.1 0.2 0.3 0 0.1 0.2 VOL (V) c.
PAGE 29
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 002aaf561 30 Isource (mA) Isource (mA) Tamb = −40 °C 25 °C 85 °C 20 002aaf562 35 Tamb = −40 °C 25 °C 85 °C 30 25 20 15 10 10 5 0 0 0 0.2 0.4 0.6 VDD(P) − VOH (V) a. VDD(P) = 1.65 V 0 002aaf563 Isource (mA) Tamb = −40 °C 25 °C 85 °C 40 0.4 0.6 VDD(P) − VOH (V) b. VDD(P) = 1.8 V 60 Isource (mA) 0.2 002aaf564 70 Tamb = −40 °C 25 °C 85 °C 60 50 40 30 20 20 10 0 0 0 0.2 0.4 0.
PAGE 30
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander VOL (mV) 002aah056 120 100 002aah057 200 VDD(P) − VOH (mV) 160 (1) 80 120 VDD(P) = 1.8 V 5V 60 (2) 80 40 (4) 20 0 −40 40 (3) −15 10 35 60 85 Tamb (°C) 0 −40 −15 10 35 60 85 Tamb (°C) Isource = 10 mA (1) VDD(P) = 1.8 V; Isink = 10 mA (2) VDD(P) = 5 V; Isink = 10 mA (3) VDD(P) = 1.8 V; Isink = 1 mA (4) VDD(P) = 5 V; Isink = 1 mA Fig 29.
PAGE 31
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 14. Dynamic characteristics Table 24. I2C-bus interface timing requirements Over recommended operating free air temperature range, unless otherwise specified. See Figure 31. Conditions Standard-mode I2C-bus Fast-mode I2C-bus Symbol Parameter Unit Min Max Min Max fSCL SCL clock frequency 0 100 0 400 tHIGH HIGH period of the SCL clock 4 - 0.6 - s tLOW LOW period of the SCL clock 4.7 - 1.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Table 26. Switching characteristics Over recommended operating free air temperature range; CL  100 pF; unless otherwise specified. See Figure 33.
PAGE 33
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander VDD(I2C-bus) RL = 4.7 kΩ INT DUT CL = 100 pF 002aag979 a.
PAGE 34
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 500 Ω Pn DUT 2 × VDD(P) CL = 50 pF 500 Ω 002aag981 a. P port load configuration SCL P0 A P7 0.7 × VDD(I2C-bus) 0.3 × VDD(I2C-bus) SDA tv(Q) Pn unstable data last stable bit A P7 002aag982 b. Write mode (R/W = 0) SCL P0 0.7 × VDD(I2C-bus) 0.3 × VDD(I2C-bus) tsu(D) th(D) Pn 0.5 × VDD(P) 002aag983 c. Read mode (R/W = 1) CL includes probe and jig capacitance. tv(Q) is measured from 0.
PAGE 35
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander VDD(I2C-bus) RL = 1 kΩ SDA DUT 500 Ω Pn DUT CL = 50 pF 2 × VDD(P) CL = 50 pF 500 Ω 002aag977 002aag981 a. SDA load configuration b. P port load configuration START SCL ACK or read cycle SDA 0.3 × VDD(I2C-bus) trst RESET 0.5 × VDD(I2C-bus) trec(rst) tw(rst) trec(rst) trst Pn 0.5 × VDD(P) 002aag984 c. RESET timing CL includes probe and jig capacitance.
PAGE 36
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 16.
PAGE 37
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
PAGE 41
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 17.
PAGE 42
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 39. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”.
PAGE 43
PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 18.
PAGE 44
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 19. Abbreviations Table 29. Abbreviations Acronym Description ESD ElectroStatic Discharge FET Field-Effect Transistor GPIO General-Purpose Input/Output I2C-bus Inter-Integrated Circuit bus I/O Input/Output LED Light-Emitting Diode LSB Least Significant Bit MSB Most Significant Bit PCB Printed-Circuit Board POR Power-On Reset SMBus System Management Bus 20. Revision history Table 30.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 Agile I/O features . . . . . . . . . . . . . . . . . . . . . . . 3 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . .