Datasheet

PCA9703 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 September 2014 7 of 28
NXP Semiconductors
PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
7.1.5 Register access timing
Figure 4 shows the waveforms of the device operation. Initially CS is HIGH and SCLK is
LOW. On the falling edge of CS
, input port status, DATA[n:0] is captured into the input
status register, and subsequently the first rising edge of SCLK parallel loads the shift
register. The falling edge of SCLK samples the data on the SDIN. The MSB from the shift
register is valid and available on the SDOUT after the first rising edge of SCLK.
7.1.6 Software reset operation
Software reset will be activated by writing all zeroes into the shift register. This is identical
to having an interrupt mask value of 0X00. Such an operation will reset the device, clear
the input status register to zero and set the interrupt output to HIGH (no interrupt).
7.2 Interrupt output
INT is the open-drain interrupt output and is active LOW. A pull-up resistor of
approximately 10 k is recommended.
A user-defined interrupt mask bit pattern is shifted into the shift register via SDIN. The
value of bits in the mask pattern will determine which input pins will cause an interrupt.
Any bit that is = 0 will disable the input pin corresponding to that bit position from
generating an interrupt. Interrupts will be enabled for bits having value = 1. The mask bit
pattern is not automatically aligned with the desired input pins. It is the responsibility of the
programmer to shift the correct number of (mask) bits to the correct positions into the shift
DATA[15:0] is data on the input pins, IN[15:0].
Shaded areas indicate active but invalid data.
Fig 4. Register access timing
CS
SCLK
SDIN
SDOUT
high-impedance
MSB in
MSB out
002aae286
MSB − 1 in
MSB − 1 out
LSB in
LSB out
input status
register
shift
register
DATA[15:0]
DATA[15:0]
sample
SDIN
interrupt mask
register