Datasheet

PCA9703 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 September 2014 15 of 28
NXP Semiconductors
PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
11. Dynamic characteristics
Table 6. Dynamic characteristics
V
DD
= 4.5 V to 5.5 V; V
SS
=0V; T
amb
=  40  C to +125  C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
f
max
maximum input clock frequency - - 5 MHz
t
r
rise time SDOUT; 10 % to 90 % at 5 V - 35 60 ns
t
f
fall time SDOUT; 90 % to 10 % at 5 V - 25 50 ns
t
WH
pulse width HIGH SCLK 50 - - ns
t
WL
pulse width LOW SCLK 50 - - ns
t
SPILEAD
SPI enable lead time CS falling edge to SCLK rising edge 50 - - ns
t
SPILAG
SPI enable lag time SCLK falling edge to CS rising edge 50 - - ns
t
su(SDIN)
SDIN set-up time SDIN to SCLK falling edge 20 - - ns
t
h(SDIN)
SDIN hold time from SCLK falling edge 30 - - ns
t
en(SDOUT)
SDOUT enable time from CS LOW to
SDOUT low-impedance; Figure 15
--55ns
t
dis(SDOUT)
SDOUT disable time from rising edge of CS to SDOUT
high-impedance; Figure 15
--85ns
t
v(SDOUT)
SDOUT valid time from rising edge of SCLK; Figure 16 --55ns
t
su(SCLK)
SCLK set-up time SCLK falling to CS falling 50 - - ns
t
h(SCLK)
SCLK hold time SCLK rising after CS rising 50 - - ns
t
POR
power-on reset pulse time time before CS is active
after V
DD
>V
POR
- - 250 ns
t
rel(int)
interrupt release time after CS going LOW; Figure 17 - - 500 ns
t
v(INT)
valid time on pin INT after INn changes or INT_EN
goes HIGH
- 200 800 ns
Fig 12. Timing diagram
CS
SCLK
SDIN
SDOUT
INT
t
SPILAG
t
WL
t
WH
high-impedance
t
SPILEAD
MSB in
MSB out
002aac428
t
su(SDIN)
t
h(SDIN)
t
en(SDOUT)
t
v(SDOUT)
t
dis(SDOUT)
t
rel(int)
50 % 50 %
t
su(SCLK)
t
h(SCLK)