Datasheet

PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 4 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
On power-up or RESET, all registers return to default values.
Fig 2. Simplified schematic of the I/Os (IO0_0 to IO4_7)
V
DD
IOx_y
I/O
configuration
register
DQ
CK Q
data from
shift register
write configuration
pulse
output port
register
DQ
CK
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
(Ix[y])
polarity inversion
register data
(Px[y])
002aab936
FF
FF
FF
FF
STOP
pulse
OCH
DQ
CK
data from
shift register
write pulse
FF
OE
OEPOL
configuration port register data (Cx[y])
output port register data (Ox[y])
INTERRUPT
MANAGEMENT
INT
Mx[y]
OUTx