Datasheet

PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 39 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
13. Test information
Fig 39. Reset timing
SDA
SCL
002aac01
8
t
rst
50 %
30 %
50 % 50 %
50 %
t
rec(rst)
t
w(rst)
RESET
IOx_y
output off
START
t
rst
ACK or read cycle
R
L
= load resistance.
C
L
= load capacitance includes jig and probe capacitance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generators.
Fig 40. Test circuitry for switching times
PULSE
GENERATOR
V
O
C
L
50 pF
R
L
500 Ω
002aac01
9
R
T
V
I
V
DD
DUT
2V
DD
open
V
SS
500 Ω