Datasheet

Product data sheet Rev. 3 — 3 August 2010 15 of 48

NXP Semiconductors

PCA9698

40-bit Fm+ I

C-bus advanced I/O port with RESET, OE and INT

• If ALLBNK = 1XX0 1100:

All I/Os configured as outputs in Bank 2 and 3 will be programmed with 1s, overwriting

values programmed in the Output Port registers 2 and 3, while I/Os configured as

outputs in Bank 0, 1, and 4 are programmed with values in Output Port registers 0, 1,

and 4.

7.4.8 MODE - PCA9698 mode selection register

This register allows programming of the PCA9698 modes.

• OEPOL bit controls the polarity of OE pin.

– OEPOL = 0: OE

pin is active LOW.

– OEPOL = 1: OE

pin is active HIGH (equivalent to OE pin).

• OCH bit selects the I

C-bus event where the state of the I/Os configured as outputs

change.

– OCH = 0: outputs change on STOP command.

– OCH = 1: outputs change on ACK.

• IOAC bit controls the ability of the device to respond to a ‘GPIO All Call’ command

(see Section 7.6 “

GPIO All Call” for more information), allowing programming of more

than one device at the same time.

– IOAC = 0: The device cannot respond to a ‘GPIO All Call’ command.

– IOAC = 1: The device can respond to a ‘GPIO All Call’ command.

Remark: The ‘GPIO ALL CALL’ command defined for the PCA9698 is different from

the I

C-bus protocol ‘General Call’ command.

• SMBA bit controls the capability of the PCA9698 to respond to a SMBAlert command.

– SMBA = 0: PCA9698 does not respond to an Alert Response Address.

– SMBA = 1: PCA9698 responds to an Alert Response Address. Bits 5, 6 and 7 are

reserved and must be programmed with 0s.

• Unused bits (bits 2, 5, 6 and 7) must be programmed with 0s for proper device

operation.

Table 11. MODE - mode selection register (address 2Ah) description

Bit 7 6 5 4 3 2 1 0

Symbol X X X SMBA IOAC X OCH OEPOL

Default 00000010