Datasheet

Product data sheet Rev. 3 — 3 August 2010 13 of 48

NXP Semiconductors

PCA9698

40-bit Fm+ I

C-bus advanced I/O port with RESET, OE and INT

7.4.5 MSK0 to MSK4 - Mask interrupt registers

These registers mask the interrupt due to a change in the I/O pins configured as inputs.

‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).

Mx[y] = 0: A level change at the I/O will generate an interrupt if IOx_y defined as input

(Cx[y] in IOC register = 1).

Mx[y] = 1: A level change in the input port will not generate an interrupt if IOx_y defined

as input (Cx[y] in IOC register = 1).

7.4.6 OUTCONF - output structure configuration register

This register controls the configuration of the output ports as open-drain or totem-pole.

The 4 least significant bits control the output architecture for bank 0, 2 bits at a time.

OUT001 controls the output structure for IO0_0 and IO0_1

OUT023 controls the output structure for IO0_2 and IO0_3

OUT045 controls the output structure for IO0_4 and IO0_5

OUT067 controls the output structure for IO0_6 and IO0_7

The 4 most significant bits control the output architectures for bank 1 to bank 4, each bit

controlling one bank.

OUT1 controls the output structure for bank 1 (IO1_0 to IO1_7)

OUT2 controls the output structure for bank 2 (IO2_0 to IO2_7)

OUT3 controls the output structure for bank 3 (IO3_0 to IO3_7)

OUT4 controls the output structure for bank 4 (IO4_0 to IO4_7)

OUTx = 0: The I/Os are configured with an open-drain structure.

OUTx = 1: The I/Os are configured with a totem-pole structure.

Table 8. MSK0 to MSK4 - Mask interrupt registers (address 20h to 24h) bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

20h MSK0 7 to 0 M0[7:0] R/W 1111 1111* Mask Interrupt register bank 0

21h MSK1 7 to 0 M1[7:0] R/W 1111 1111* Mask Interrupt register bank 1

22h MSK2 7 to 0 M2[7:0] R/W 1111 1111* Mask Interrupt register bank 2

23h MSK3 7 to 0 M3[7:0] R/W 1111 1111* Mask Interrupt register bank 3

24h MSK4 7 to 0 M4[7:0] R/W 1111 1111* Mask Interrupt register bank 4

Table 9. OUTCONF - output structure configuration register (address 28h) description

Bit 7 6 5 4 3 2 1 0

Symbol OUT4 OUT3 OUT2 OUT1 OUT067 OUT045 OUT023 OUT001

Default 11111111