Datasheet

PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 12 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
7.4.3 PI0 to PI4 - Polarity Inversion registers
These registers allow inversion of the polarity of the corresponding Input Port register.
Px[y] = 0: The corresponding Input Port register data polarity is retained.
Px[y] = 1: The corresponding Input Port register data polarity is inverted.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
7.4.4 IOC0 to IOC4 - I/O Configuration registers
These registers configure the direction of the I/O pins.
Cx[y] = 0: The corresponding port pin is an output.
Cx[y] = 1: The corresponding port pin is an input.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Table 6. PI0 to PI4 - Polarity Inversion registers (address 10h to 14h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
10h PI0 7 to 0 P0[7:0] R/W 0000 0000* Polarity Inversion register bank 0
11h PI1 7 to 0 P1[7:0] R/W 0000 0000* Polarity Inversion register bank 1
12h PI2 7 to 0 P2[7:0] R/W 0000 0000* Polarity Inversion register bank 2
13h PI3 7 to 0 P3[7:0] R/W 0000 0000* Polarity Inversion register bank 3
14h PI4 7 to 0 P4[7:0] R/W 0000 0000* Polarity Inversion register bank 4
Table 7. IOC0 to IOC4 - I/O Configuration registers (address 18h to 1Ch) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
18h IOC0 7 to 0 C0[7:0] R/W 1111 1111* I/O Configuration register bank 0
19h IOC1 7 to 0 C1[7:0] R/W 1111 1111* I/O Configuration register bank 1
1Ah IOC2 7 to 0 C2[7:0] R/W 1111 1111* I/O Configuration register bank 2
1Bh IOC3 7 to 0 C3[7:0] R/W 1111 1111* I/O Configuration register bank 3
1Ch IOC4 7 to 0 C4[7:0] R/W 1111 1111* I/O Configuration register bank 4