Datasheet

PCA9674_PCA9674A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 30 May 2013 16 of 40
NXP Semiconductors
PCA9674; PCA9674A
Remote 8-bit I/O expander for Fm+ I
2
C-bus with interrupt
Simple code for Write cycle:
<S> <slave address + W> <ACK> <DATA1> <ACK> <DATA2> <ACK> <DATA1> ...
<DATA2> <ACK> <P>
8.3 Reading from a port (Input mode)
The port must have been previously written to logic 1, which is the condition after
power-on reset or software reset. To enter the Read mode the master (microcontroller)
addresses the slave device and sets the last bit of the address byte to logic 1 (address
byte read). The slave will acknowledge and then send the data byte to the master. The
master will NACK and then send the STOP condition or ACK and read the input register
again.
The read of any pin being used as an output will indicate HIGH or LOW depending on the
actual state of the pin.
If the data on the input port changes faster than the master can read, this data may be
lost. The DATA 2 and DATA 3 are lost because these data did not meet the set-up time
and hold time (see Figure 14
).
Simple code for Read cycle:
<S> <slave address + R> <ACK> <DATA in> <ACK> <DATA in> ... <NACK> <P>
A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at
any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (Output mode). Input
data is lost.
Fig 14. Read input port register
A5 A4 A3 A2 A1 A0 1 ASA6
slave address
START condition R/W acknowledge
from slave
002aah383
data from port
A
acknowledge
from master
SDA 1
no acknowledge
from master
read from
port
data at
port
data from port
DATA 1
DATA 4
INT
DATA 4
DATA 2
DATA 3
P
STOP
condition
t
v(INT)
t
rst(INT)
t
h(D)
t
su(D)
t
rst(INT)
DATA 1