Datasheet
PCA9672 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 27 May 2013 21 of 36
NXP Semiconductors
PCA9672
Remote 8-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
[1] t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
[3] C
b
= total capacitance of one bus line in pF.
[4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
IL
of the SCL signal) in order to
bridge the undefined region SCL’s falling edge.
[5] The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
f
.
[6] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
Port timing; C
L
100 pF (see Figure 13 and Figure 14)
t
v(Q)
data output valid time - 4 - 4 - 4 s
t
su(D)
data input set-up time 0 - 0 - 0 - s
t
h(D)
data input hold time 4 - 4 - 4 - s
Interrupt timing; C
L
100 pF (see Figure 13 and Figure 14)
t
v(INT)
valid time on pin INT from port
to INT
-4 - 4-4s
t
rst(INT)
reset time on pin INT from SCL
to INT
-4 - 4-4s
Reset timing (see Figure 23
)
t
w(rst)
reset pulse width 4 - 4 - 4 - s
t
rec(rst)
reset recovery time 0 - 0 - 0 - s
t
rst
reset time 100 - 100 - 100 - s
Table 9. Dynamic characteristics …continued
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
Cto+85
C; unless otherwise specified.
Symbol Parameter Conditions Standard mode
I
2
C-bus
Fast mode I
2
C-bus Fast mode Plus
I
2
C-bus
Unit
Min Max Min Max Min Max
Rise and fall times refer to V
IL
and V
IH
.
Fig 22. I
2
C-bus timing diagram
002aab175
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
SCL
SDA
t
HD;STA
t
SU;DAT
t
HD;DAT
t
f
t
BUF
t
SU;STA
t
LOW
t
HIGH
t
VD;ACK
t
SU;STO
1
/ f
SCL
t
r
t
VD;DAT
0.3 × V
DD
0.7 × V
DD
0.3 × V
DD
0.7 × V
DD