Datasheet
PCA9672 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 27 May 2013 20 of 36
NXP Semiconductors
PCA9672
Remote 8-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
[1] The power-on reset circuit resets the I
2
C-bus logic with V
DD
<V
POR
and set all I/Os to logic 1 (with current source to V
DD
).
[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits.
[3] The value is not tested, but verified on sampling basis.
14. Dynamic characteristics
Inputs AD0, AD1
V
IL
LOW-level input voltage 0.5 - +0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
-5.5V
I
LI
input leakage current 1- +1 A
C
i
input capacitance - 3 5 pF
Table 8. Static characteristics
…continued
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
Cto+85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Table 9. Dynamic characteristics
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
Cto+85
C; unless otherwise specified.
Symbol Parameter Conditions Standard mode
I
2
C-bus
Fast mode I
2
C-bus Fast mode Plus
I
2
C-bus
Unit
Min Max Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 0 1000 kHz
t
BUF
bus free time between a
STOP and START
condition
4.7 - 1.3 - 0.5 - s
t
HD;STA
hold time (repeated)
START condition
4.0 - 0.6 - 0.26 - s
t
SU;STA
set-up time for a repeated
START condition
4.7 - 0.6 - 0.26 - s
t
SU;STO
set-up time for STOP
condition
4.0 - 0.6 - 0.26 - s
t
HD;DAT
data hold time 0 - 0 - 0 - ns
t
VD;ACK
data valid acknowledge
time
[1]
0.3 3.45 0.1 0.9 0.05 0.45 s
t
VD;DAT
data valid time
[2]
300 - 50 - 50 450 ns
t
SU;DAT
data set-up time 250 - 100 - 50 - ns
t
LOW
LOW period of the SCL
clock
4.7 - 1.3 - 0.5 - s
t
HIGH
HIGH period of the SCL
clock
4.0 - 0.6 - 0.26 - s
t
f
fall time of both SDA and
SCL signals
[4][5]
-30020+0.1C
b
[3]
300 - 120 ns
t
r
rise time of both SDA and
SCL signals
- 1000 20 + 0.1C
b
[3]
300 - 120 ns
t
SP
pulse width of spikes that
must be suppressed by the
input filter
[6]
-50 - 50-50ns