Datasheet

PCA9616 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 10 March 2014 9 of 32
NXP Semiconductors
PCA9616
3-channel multipoint Fm+ dI
2
C-bus buffer with hot-swap logic
connection is established between the differential and the single-ended buses. Whenever
disconnected status is detected or the device is un-powered, the PCA9616 will disconnect
the single-ended to differential buses, and the hot swap sequence will repeat again before
the PCA9616 connects SDA to DSDAP/DSDAM and SCL to DSCLP/DSCLM.
Remark: Start-up process is the same for both PCA9616PW and PCA9615DP, except
that PIDET
and READY signals are only available in 16-pin package.
For PCA9616, the READY time is at least 11 ms (1 ms for power ready, 10 ms for
plug-in debouncing delay), which means the device can only be in operation after 11 ms
with V
DD(A)
,V
DD(B)
ON and a bus idle/stop detected.
Fig 6. Hot swap related timings
~11 ms
~1 ms
t
en
for power-on
and stabilization
V
DD(A)
, V
DD(B)
pwon
~10 ms
PIDET
EN
only when EN goes HIGH
and PIDET inputs go LOW
will the bus idle/stop detector
start functioning
t
idle
SCL/SDA,
DSCL/DSDA
t
stop
READY = pwon && PIDET && EN &&
002aah591
(set by bus idle or stop)
plug-in debouncing time