Datasheet

PCA9616 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 10 March 2014 8 of 32
NXP Semiconductors
PCA9616
3-channel multipoint Fm+ dI
2
C-bus buffer with hot-swap logic
7.3 EN pin
Enable input to connect the device into bus. When this pin is LOW, the device will never
connect to the bus, and disconnect the SCL/SDA from differential SCL/SDA, and READY
pin set HIGH. When EN is driven HIGH, and V
DD(A)
and V
DD(B)
are stable and dI
2
C-bus
side are with appropriate loads (indicated by PIDET
goes LOW), the EN pin connects
SDA/SCL to differential SDA/SCL after a stop bit or bus idle has been detected on
differential line bus. EN pin should never change state during an I
2
C-bus/SMBus
operation because disabling during a bus operation will hang the bus and enabling part
way through a bus cycle could confuse the I
2
C-bus/SMBus parts being enabled. The EN
pin should only change state when the global bus and the buffer port are in an idle state to
prevent system failures.
7.4 PIDET pin
Plug-in status output. This open-drain N-channel MOSFET output pulls LOW when the
hot-swapped pins (differential SDA and SCL) have been steady and reliably plugged into
the bus when V
DD(A)
and V
DD(B)
are powered. Connect a pull-up resistor, typically 10 k,
from this pin to V
DD(A)
. Leave open or tie to V
SS
if unused.
7.5 READY pin
Connection ready status output. This open-drain N-channel MOSFET output goes HIGH
when the input and output sides are disconnected. READY
is pulled LOW when EN is
HIGH, PIDET
is LOW, and a connection has been established between the input and
differential output. Connect a pull-up resistor, typically 10 k, from this pin to V
DD(A)
.
Leave open or tie to V
SS
if unused.
7.6 VDDA_SEL pin
Enable input to select V
DD(A)
range. Tie to V
DD(B)
if V
DD(A)
is greater than 2.2 V and
constant V
OL
on SCL/SDA (0.52 V) is desired, and tie to V
SS
if V
DD(A)
is less than 2.4 V
and the ratio V
OL
(0.2  V
DD(A)
) is desired. Or leave open to let the device automatically
switch based on V
DD(A)
magnitude.
7.7 Hot swap and power-on reset
During a power-on sequence, an initialization circuit holds the PCA9616 in a disconnected
state, meaning all outputs — SDA, SCL and the differential pins DSCLP/DSCLM and
DSDAP/DSDAM — are in a high-impedance state. As the power supply rises (either
power-up or live insertion), the initialization circuit enters a state where the internal
references are stabilized and an internal timer is triggered. After 1 ms, power is applied to
the rest of the circuitry and the PCA9616 detects the status on the differential
DSCLP/DSCLM and DSDAP/DSDAM lines. When the differential lines are detected as
connected to a bus with valid termination, that is, both DSCLM/DSDAM < 0.9  V
DD(B)
and
DSCLP/DSDAP > 0.1  V
DD(B)
, another timer is triggered. At the end of 10 ms, hot-swap
logic (Figure 2
) is enabled and the EN pin can detect a Stop Bit and Bus Idle condition.
However, there is still no connection between SDA and DSDAP/DSDAM or between SCL
and DSCLP/DSCLM. A successful EN pin sequence must occur for actual connection.
When the EN pin is set HIGH and the DSDAP and DSCLP pins have been HIGH for the
bus idle time or when both the SCL and SDA pins are HIGH and a STOP condition has
been seen on the differential bus (DSDAP/DSDAM and DSCLP/DSCLM pins), a