Datasheet
PCA9616 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 10 March 2014 2 of 32
NXP Semiconductors
PCA9616
3-channel multipoint Fm+ dI
2
C-bus buffer with hot-swap logic
2. Features and benefits
New dI
2
C-bus buffers offer improved resistance to system noise and ground offset
up to
1
⁄
2
of supply voltage
Hot swap (allows insertion or removal of modules or card without disruption to bus
data)
READY
signal (PCA9616 output) indicates device is ready from a cold start
EN signal (PCA9616 input) controls PCA9616 hot swap sequence
Bus idle detect (PCA9616 internal function) waits for a bus idle condition before
connection is made
3 channel dI
2
C (differential I
2
C-bus) to Fm+ single-ended buffer operating up to 1 MHz
with 30 mA SDA/SCL > 2.2 V, or 3 mA SDA/SCL < 2.4 V
Compatible with I
2
C-bus Standard/Fast-mode and SMBus, Fast-mode Plus up to
1MHz
Active HIGH (internal pull-up resistor) Enable disables the device to high-impedance
state
Single-ended I
2
C-bus on card side up to 540 pF >2.2 V and 400 pF <2.4 V
Differential I
2
C-bus on cable side supporting multi-drop bus
Maximum cable length: 3 m (approximately 10 feet) (longer at lower frequency)
dI
2
C output: 1.5 V differential output with nominal terminals
Differential line impedance (user defined): 100 nominal suggested
Receive input sensitivity: 200 mV
Hysteresis: 30 mV typical
Input impedance: high-impedance (200 k typical)
Receive input voltage range: 0.5 V to +5.5 V
Lock-up free operation
Supports arbitration and clock stretching across the dI
2
C-bus buffers
Powered-off and powering-up high-impedance I
2
C-bus pins
Operating supply voltage (V
DD(A)
) range of 0.8 V to 5.5 V with single-ended side 5.5 V
tolerant
Fig 1. SMBus/I
2
C-bus translation to dI
2
C-bus and back to SMBus/I
2
C-bus
V
DD(A)1
SCL
SDA
PCA9616
aaa-009537
dI
2
C-bus
(differential I
2
C-bus,
1 of 3 lines shown)
twisted-pair cable
single-ended
I
2
C-bus
PCA9616
SCL
SDA
GND1 GND2
V
DD(A)2
single-ended
I
2
C-bus
V
DD(B)
V
DD(B)
INT
INT
V
DD(B)
V
DD(B)
PIDET
PIDET
READY
READY
EN
EN