Datasheet
PCA9614 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 11 April 2014 2 of 27
NXP Semiconductors
PCA9614
2-channel multipoint Fm+ differential I
2
C-bus buffer
2. Features and benefits
New dI2C-bus buffers offer improved resistance to system noise and ground offset up
to
1
⁄
2
of supply voltage
2 channel dI
2
C (differential I
2
C) to Fm+ single-ended buffer operating up to 1 MHz with
30 mA SDA/SCL drive capability
Compatible with I
2
C-bus Standard/Fast-mode and SMBus, Fast-mode Plus up to
1MHz
Active HIGH (internal pull-up resistor) Enable disables devices to high-impedance
state
Single-ended I
2
C-bus on card side up to 540 pF
Differential I
2
C-bus on cable side supporting multi-drop bus
Maximum cable length: 3 m (approximately 10 feet) (longer at lower frequency)
dI
2
C output: 1.5 V differential output with nominal terminals
Differential line impedance (user defined): 100 nominal suggested
Receive input sensitivity: 200 mV
Hysteresis: 30 mV typical
Input impedance: high-impedance (1 M typical)
Receive input voltage range: 0.5 V to +5.5 V
Lock-up free operation
Supports arbitration and clock stretching across the dI
2
C-bus buffers
Powered-off and powering-up high-impedance I
2
C-bus pins
Operating supply voltage (V
DD(A)
) range of 2.3 V to 5.5 V with single-ended side 5.5 V
tolerant
Differential I
2
C-bus operating supply voltage (V
DD(B)
) range of 3.0 V to 5.5 V with
5.5 V tolerant. Best operation is at 5 V.
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Package offering: TSSOP10
Fig 1. SMBus/I
2
C-bus translation to dI
2
C-bus and back to SMBus/I
2
C-bus
V
DD(A)1
SCL
SDA
PCA9614
aaa-011060
dI
2
C-bus
(differential I
2
C-bus,
1 of 2 lines shown)
twisted-pair cable
single-ended
I
2
C-bus
PCA9614
SCL
SDA
GND1 GND2
V
DD(A)2
single-ended
I
2
C-bus
V
DD(B)
V
DD(B)
EN
EN
V
DD(B)
V
DD(B)