Datasheet

PCA9601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 6 May 2011 5 of 32
NXP Semiconductors
PCA9601
Dual bidirectional bus buffer
7.2 High drive, long distance side
The logic level on RX is determined from the power supply voltage V
CC
of the chip. Logic
LOW is below 40 % of V
CC
, and logic HIGH is above 55 % of V
CC
(with a typical switching
threshold just slightly below half V
CC
).
TX is an open-collector output without ESD protection diodes to V
CC
. It may be connected
via a pull-up resistor to a supply voltage in excess of V
CC
, as long as the 15 V rating is not
exceeded. It has a larger current sinking capability than a normal I
2
C-bus device, being
able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down
capability as well.
A logic LOW is transmitted to TX when the voltage at I
2
C-bus pin SX is below 0.425 V. A
logic LOW at RX will cause I
2
C-bus pin SX to be pulled to a logic LOW level in accordance
with I
2
C-bus requirements (maximum 1.5 V in 5 V applications) but not low enough to be
looped back to the TX output and cause the buffer to latch LOW.
The LOW level this chip can achieve on the I
2
C-bus by a LOW at RX is typically 0.64 V
when sinking 1 mA.
If the supply voltage V
CC
fails, then neither the I
2
C-bus nor the TX output will be held
LOW. Their open-collector configuration allows them to be pulled up to the rated
maximum of 15 V even without V
CC
present. The input configuration on SX and RX also
presents no loading of external signals when V
CC
is not present.
The effective input capacitance of any signal pin, measured by its effect on bus rise times,
is less than 10 pF for all bus voltages and supply voltages including V
CC
=0V.
7.3 Connections to other bus buffers
Two or more SX or SY I/Os must not be interconnected. The PCA9601 design does not
support this configuration. Bidirectional I
2
C-bus signals do not allow any direction control
pin so, instead, slightly different logic LOW voltage levels are used at SX/SY to avoid
latching of this buffer. A ‘regular I
2
C-bus LOW’ applied at the RX/RY of a PCA9601 will be
propagated to SX/SY as a ‘buffered LOW’ with a slightly higher voltage level. If this special
‘buffered LOW’ is applied to the SX/SY of another PCA9601, that second PCA9601 will
not recognize it as a ‘regular I
2
C-bus LOW’ and will not propagate it to its TX/TY output.
The SX/SY side of PCA9601 may not be connected to similar buffers that rely on special
logic thresholds for their operation, for example P82B96, PCA9511A, PCA9515A, ‘B’ side
of PCA9517, etc. The SX/SY side is only intended for, and compatible with, the normal
I
2
C-bus logic voltage levels of I
2
C-bus master and slave chips, or even TX/RX signals of a
second PCA9601 or P82B96 if required. The TX/RX and TY/RY I/O pins use the standard
I
2
C-bus logic voltage levels of all I
2
C-bus parts. There are no restrictions on the
interconnection of the TX/RX and TY/RY I/O pins to other PCA9601s, for example in a
star or multipoint configuration with the TX/RX and TY/RY I/O pins on the common bus
and the SX/SY side connected to the line card slave devices. For more details see
Application Note AN10658, “Sending I
2
C-bus signals via long communication cables”.