Datasheet
PCA9601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 6 May 2011 10 of 32
NXP Semiconductors
PCA9601
Dual bidirectional bus buffer
[1] This bus pull-up current specification is intended to assist design of the bus pull-up resistor. It is not a specification of the sink capability
(see V
OL
under sub-section “Output logic LOW level”). When used on an Fm+ bus the load current is limited to 15 mA by the drive
capability of PCA9601. When used in a standard I
2
C-bus the load current is limited by the drive capability of other devices on the bus.
The maximum static sink current for a Standard/Fast-mode I
2
C-bus is 3 mA and PCA9601 is guaranteed to sink more than 3 mA at
SX/SY when its pins are holding the bus LOW. However, when an external device pulls the SX/SY pins below 1.4 V, the PCA9601 will
source a current between 0 mA and 1 mA maximum. When that other external device is driving LOW it will pull the bus connected to SX
or SY down to, or below, the 0.4 V level referenced in the I
2
C-bus specification and in these test conditions. Then that device must be
able to sink up to 1 mA coming from SX/SY plus the usual pull-up current. Therefore in Standard and Fast-mode systems the external
pull-up used at SX/SY should be limited to 2 mA. The typical and maximum currents sourced by SX/SY as a function of junction
temperature are shown in Figure 10
, and the equivalent circuit at the SX/SY interface is shown in Figure 4.
[2] Valid over temperature for V
CC
≤ 5 V. At higher V
CC
, this current may increase to maximum −20 μA at V
CC
=15V.
[3] The input logic threshold is independent of the supply voltage.
[4] The minimum value requirement for pull-up current, 0.3 mA, guarantees that the minimum value for V
SX
output LOW will always exceed
the maximum V
SX
input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any
IC. While the tolerances on absolute levels allow a small probability, the LOW from one SX output is recognized by an SX input of
another PCA9601, this has no consequences for normal applications. In any design the SX pins of different ICs should never be linked
because the resulting system would be very susceptible to induced noise and would not support all I
2
C-bus operating modes.
[5] The fall time of V
TX
from 5 V to 2.5 V in the test is approximately 10 ns.
The fall time of V
SX
from 5 V to 2.5 V in the test is approximately 20 ns.
The rise time of V
TX
from 0 V to 2.5 V in the test is approximately 15 ns.
The rise time of V
SX
from 0.7 V to 2.5 V in the test is approximately 25 ns.
Buffer response time
[5]
V
CC
= 5 V; pin TX pull-up resistor = 160 Ω; pin SX pull-up resistor = 2.2 kΩ; no capacitive load
t
d
delay time V
SX
to V
TX
, V
SY
to V
TY
; on falling
input between V
SX
= input switching
threshold, and V
TX
output falling to
50 % V
CC
-50-ns
V
SX
to V
TX
, V
SY
to V
TY
; on rising
input between V
SX
= input switching
threshold, and V
TX
output reaching
50 % V
CC
-60-ns
V
RX
to V
SX
, V
RY
to V
SY
; on falling
input between V
RX
= input switching
threshold, and V
SX
output falling to
50 % V
CC
- 100 - ns
V
RX
to V
SX
, V
RY
to V
SY
; on rising
input between V
RX
= input switching
threshold, and V
SX
output reaching
50 % V
CC
-95-ns
Input capacitance
C
i
input capacitance effective input capacitance of any
signal pin measured by incremental
bus rise times; guaranteed by
design, not production tested
--10pF
Table 6. Characteristics
…continued
T
amb
=
−
40
°
C to +85
°
C unless otherwise specified; voltages are specified with respect to GND with V
CC
= 2.5 V to 15 V
unless otherwise specified. Typical values are measured at V
CC
= 5 V and T
amb
=25
°
C.
Symbol Parameter Conditions Min Typ Max Unit