Datasheet

PCA9600 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 5 May 2011 4 of 31
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
The logic threshold voltage levels at SX on this I
2
C-bus are independent of the IC supply
voltage V
CC
. The maximum I
2
C-bus supply voltage is 15 V.
When interfacing with Fast-mode systems, the SX pin is guaranteed to sink the normal
3 mA with a V
OL
of 0.74 V maximum. That guarantees compliance with the Fast-mode
I
2
C-bus specification for all I
2
C-bus voltages greater than 3 V, as well as compliance with
SMBus or other systems that use TTL switching levels.
SX is guaranteed to sink an external 3 mA in addition to its internally sourced pull-up of
typically 300 μA (maximum 1 mA at −40 °C). When selecting the pull-up for the bus at SX,
the sink capability of other connected drivers should be taken into account. Most TTL
devices are specified to sink at least 4 mA so then the pull-up is limited to 3 mA by the
requirement to ensure the 0.8 V TTL LOW.
For Fast-mode I
2
C-bus operation, the other connected I
2
C-bus parts may have the
minimum sink capability of 3 mA. SX sources typically 300 μA (maximum 1 mA at −40 °C),
which forms part of the external driver loading. When selecting the pull-up it is necessary
to subtract the SX pin pull-up current, so, worst-case at −40 °C, the allowed pull-up can be
limited (by external drivers) to 2 mA.
When the interface at SX is an Fm+ bus with a voltage greater than 4 V, its higher
specified sink capability may be used. PCA9600 has a guaranteed sink capability of 7 mA
at V
OL
= 1 V maximum. That 1 V complies with the bus LOW requirement (0.25V
bus
) of
any Fm+ bus operating at 4 V or greater. Since the other connected Fm+ devices have a
drive capability greater than 20 mA, the pull-up may be selected for 7 mA sink current at
V
OL
= 1 V. For a nominal 5 V bus (5.5 V maximum) the allowed pull-up is
(5.5 V − 1V)/7mA=643Ω. With 680 Ω pull-up, the Fm+ rise time of 120 ns maximum
can be met with total bus loading up to 200 pF.
The logic level on RX is determined from the power supply voltage V
CC
of the chip. Logic
LOW is below 40 % of V
CC
, and logic HIGH is above 55 % of V
CC
(with a typical switching
threshold just slightly below half V
CC
).
TX is an open-collector output without ESD protection diodes to V
CC
. It may be connected
via a pull-up resistor to a supply voltage in excess of V
CC
, as long as the 15 V rating is not
exceeded. It has a larger current sinking capability than a normal I
2
C-bus device, being
able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down
capability as well.
A logic LOW is transmitted to TX when the voltage at I
2
C-bus pin SX is below 0.425 V. A
logic LOW at RX will cause I
2
C-bus pin SX to be pulled to a logic LOW level in accordance
with I
2
C-bus requirements (maximum 1.5 V in 5 V applications) but not low enough to be
looped back to the TX output and cause the buffer to latch LOW.
The LOW level this chip can achieve on the I
2
C-bus by a LOW at RX is typically 0.64 V
when sinking 1 mA.
If the supply voltage V
CC
fails, then neither the I
2
C-bus nor the TX output will be held
LOW. Their open-collector configuration allows them to be pulled up to the rated
maximum of 15 V even without V
CC
present. The input configuration on SX and RX also
presents no loading of external signals when V
CC
is not present.
The effective input capacitance of any signal pin, measured by its effect on bus rise times,
is less than 10 pF for all bus voltages and supply voltages including V
CC
=0V.