Datasheet

PCA9600 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 5 May 2011 17 of 31
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
The actual LOW period will be 407 + 126 = 533 ns, which exceeds the minimum Fm+
500 ns requirement. This system requires the bus LOW period, and therefore cycle
time, to be increased by 33 ns so the system must run slightly below the 1 MHz limit.
The possible maximum speed has a cycle period of 1033 ns or 968 kHz.
There is an Excel calculator which makes it easy to determine the maximum I
2
C-bus clock
speed when using the PCA9600. The calculator and instructions can be found at
www.nxp.com/clockspeedcalculator
.
Fig 18. I
2
C-bus multipoint application
PCA9600
SDA
RX
SCL
TX
TY
RY
001aai06
5
12 V
SX
SY
12 V
12 V
3.3 V to 5 V
3.3 V to 5 V
PCA9600
SX SY
SCL/SDA
PCA9600
SX SY
SCL/SDA
PCA9600
SX SY
SCL/SDA
PCA9600
SX SCL
SY SDA
no limit to the number of connected bus devices
twisted-pair telephone wires,
USB, or flat ribbon cables;
up to 15 V logic levels,
include V
CC
and GND
3.3 V 3.3 V