Datasheet

PCA9600 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 5 May 2011 16 of 31
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
from the master reaching the slave (Figure 15) minus the effective delay (stretch) of the
SCL rising edge (Figure 16
) plus total delays in the slave's response data, carried on
SDA, reaching the master (Figure 17
).
The master microcontroller should be programmed to produce a nominal SCL LOW
period as follows:
(1)
The actual LOW period will become (the programmed value + the stretching time B).
When this actual LOW period is then less than the specified minimum, the specified
minimum should be used.
Example 1:
It is required to connect an Fm+ slave, with Rs × Cs product of 100 ns, to a 5 V
Fast-mode system also having 100 ns Rm × Cm using two PCA9600’s to buffer a 5 V
bus with 4 nF loading and 160 Ω pull-up.
Calculate the allowed bus speed:
Delay A = 120 + 85 + (2.5 + [4 × 4]) × 5 + 50 = 347.5 ns
Delay B = 115 + 100 + 70 = 285 ns
Delay C = 115 + 20 + 0.7(100 + 100) = 275 ns
The maximum Fm+ slave response delay must be < 450 ns so the programmed LOW
period is calculated as:
LOW ≥ 450 + 347.5 − 285 + 275 + 100 = 887.5 ns
The actual LOW period will be 887.5 + 285 = 1173 ns, which is below the Fast-mode
minimum, so the programmed LOW period must be increased to
(1300 − 285) = 1015 ns, so the actual LOW equals the 1300 ns requirement and this
shows that this Fast-mode system may be safely run to its limit of 400 kHz.
Example 2:
It is required to buffer a Master with Fm+ speed capability, but only 3 mA sink capability,
to an Fm+ bus. All the system operates at 3.3 V. The Master Rm × Cm product is 50 ns.
Only one PCA9600 is used. The Fm+ bus becomes the buffered bus. The Fm+ bus has
200 pF loading and 150 Ω pull-up, so its Rb × Cb product is 30 ns. The Fm+ slave has a
specified data valid time t
VD;DAT
maximum of 300 ns.
Calculate the allowed maximum system bus speed. (Note that the fixed values in the
delay equations represent the internal propagation delays of the PCA9600. Only one
PCA9600 is used here, so those fixed values used below are taken from the
characteristics.)
The delays are:
Delay A = 40 + 56 + (2.5 + [4 × 0.2]) × 3.3 = 107 ns
Delay B = 115 + 50 + 21 = 186 ns
Delay C = 70 + 0.7(50 + 30) = 126 ns
The programmed LOW period is calculated as:
SCL LOW ≥ 300 + 117 − 186 + 126 + 50 = 407 ns
SCL LOW slave response delay to valid data on it s SDA A B C data set-up time++–+( )≥ ns