Datasheet

PCA9600 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 5 May 2011 15 of 31
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
Figure 15, Figure 16, and Figure 17 show the PCA9600 used to drive extended bus wiring
with relatively large capacitances linking two I
2
C-bus nodes. It includes simplified
expressions for making the relevant timing calculations for 3.3 V or 5 V operation.
Because the buffers and the wiring introduce timing delays, it may be necessary to
decrease the nominal SCL frequency. In most cases the actual bus frequency will be
lower than the nominal Master timing due to bit-wise stretching of the clock periods.
The delay factors involved in calculation of the allowed bus speed are:
A — The propagation delay of the master signal through the buffers and wiring to the
slave. The important delay is that of the falling edge of SCL because this edge ‘requests’
the data or acknowledge from a slave. See Figure 15
.
B — The effective stretching of the nominal LOW period of SCL at the master caused by
the buffer and bus rise times. See Figure 16
.
C — The propagation delay of the slave's response signal through the buffers and wiring
back to the master. The important delay is that of a rising edge in the SDA signal. Rising
edges are always slower and are therefore delayed by a longer time than falling edges.
(The rising edges are limited by the passive pull-up while falling edges are actively
driven); see Figure 17
.
The timing requirement in any I
2
C-bus system is that a slave's data response (which is
provided in response to a falling edge of SCL) must be received at the master before the
end of the corresponding LOW period of SCL as appears on the bus wiring at the master.
Since all slaves will, as a minimum, satisfy the worst case timing requirements of their
speed class (Fast-mode, Fm+, etc.), they must provide their response, allowing for the
set-up time, within the minimum allowed clock LOW period, e.g., 450 ns (max.) for Fm+
parts. In systems that introduce additional delays it may be necessary to extend the
minimum clock LOW period to accommodate the ‘effective’ delay of the slave's response.
The effective delay of the slave’s response equals the total delays in SCL falling edge
Effective delay of SDA at master: 115 + 0.2(Rs × Cs) + 0.7[(Rb × Cb) + (Rm × Cm)] (ns).
C=F; R=Ω.
Fig 17. Rising edge of SDA at slave is delayed by the buffers and bus rise times
PCA9600 PCA9600
SDA
SX
local master bus
V
CCM
SDA
MASTER
I
2
C-BUS
Cs
slave bus
capacitance
Cb
buffered bus
wiring capacitance
Cm
master bus
capacitance
Rm
GND (0 V)
V
CCB
buffered expansion bus
TX/RX
TX/RX SX
Rb Rs
I
2
C-BUS
SLAVE
V
CCS
remote slave bus
001aai1
58