Datasheet

PCA9600 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 5 May 2011 14 of 31
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
10.1 Calculating system delays and bus clock frequency
Effective delay of SCL at slave: 120 + 17V
CCM
+(2.5+4× 10
9
× C
b
) × V
CCB
+ 10V
CCS
(ns).
C=F; V=V.
Fig 15. Falling edge of SCL at master is delayed by the buffers and bus fall times
PCA9600 PCA9600
SCL
SX
local master bus
V
CCM
SCL
MASTER
I
2
C-BUS
Cs
slave bus
capacitance
Cb
buffered bus
wiring capacitance
Cm
master bus
capacitance
Rm
GND (0 V)
V
CCB
buffered expansion bus
TX/RX
TX/RX SX
Rb Rs
I
2
C-BUS
SLAVE
V
CCS
remote slave bus
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47
Effective delay of SCL at master: 115 + (Rm × Cm) + (0.7 × Rb × Cb) (ns).
C=F; R=Ω.
Fig 16. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times
PCA9600
SX
local master bus
V
CCM
SCL
MASTER
I
2
C-BUS
Cb
buffered bus
wiring capacitance
Cm
master bus
capacitance
Rm
GND (0 V)
V
CCB
buffered expansion bus
TX/RX
TX/RX
Rb
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48