Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 7 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
6.2 Pin description
[1] HWQFN24 package die supply ground is connected to both V
SS
pin and exposed center pad. V
SS
pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad must be soldered to the board using a corresponding thermal pad on
the board and for proper heat conduction through the board, thermal vias must be incorporated in the PCB
in the thermal pad region.
Table 3. Pin description
Symbol Pin Type Description
TSSOP28 TSSOP24 HWQFN24
A0 1 - - I address input 0
V
DD
2 1 22 power supply supply voltage
RESET
3 2 23 I active LOW reset input
P0_0 4 3 24 I/O port 0 input/output 0
P0_1 5 4 1 I/O port 0 input/output 1
P0_2 6 5 2 I/O port 0 input/output 2
P0_3 7 6 3 I/O port 0 input/output 3
A1 8 - - I address input 1
V
DD(IO)0
9 7 4 power supply I/O supply voltage for bank 0
P0_4 10 8 5 I/O port 0 input/output 0
P0_5 11 9 6 I/O port 0 input/output 1
P0_6 12 10 7 I/O port 0 input/output 2
P0_7 13 11 8 I/O port 0 input/output 3
INT
14 12 9 O interrupt output (open-drain;
active LOW)
A2 15 - - I address input 2
V
SS
16 13 10
[1]
ground supply ground
P1_7 17 14 11 I/O port 1 input/output 4
P1_6 18 15 12 I/O port 1 input/output 5
P1_5 19 16 13 I/O port 1 input/output 6
P1_4 20 17 14 I/O port 1 input/output 7
V
DD(IO)1
21 18 15 power supply I/O supply voltage for bank 1
A3 22 - - I address input 3
P1_3 23 19 16 I/O port 1 input/output 3
P1_2 24 20 17 I/O port 1 input/output 2
P1_1 25 21 18 I/O port 1 input/output 1
P1_0 26 22 19 I/O port 1 input/output 0
SDA 27 23 20 I/O serial data line
SCL 28 24 21 I serial clock line