Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 6 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
6. Pinning information
6.1 Pinning
Fig 3. Pin configuration for TSSOP24 Fig 4. Pin configuration for TSSOP28
Fig 5. Pin configuration for HWQFN24
SCL
SDA
P1_0
P1_1
P1_2
P1_3
V
DD(IO)1
P1_4
P1_5
P1_6
P1_7
V
SS
V
DD(IO)0
P0_4
P0_5
P0_6
P0_7
INT
V
DD
RESET
P0_0
P0_1
P0_2
P0_3
PCA9575PW1
002aad564
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
PCA9575PW2
A0 SCL
V
DD
SDA
RESET P1_0
P0_0 P1_1
P0_1 P1_2
P0_2 P1_3
P0_3 A3
A1 V
DD(IO)1
V
DD(IO)0
P1_4
P0_4 P1_5
P0_5 P1_6
P0_6 P1_7
P0_7 V
SS
INT A2
002aad563
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
002aad575
PCA9575HF
Transparent top view
P1_5
P0_4
P0_5
P1_4
V
DD(IO)0
V
DD(IO)1
P0_3 P1_3
P0_2 P1_2
P0_1 P1_1
P0_6 P0_7
INT
V
SS
P1_7 P1_6
P0_0 RESET V
DD
SCL SDA P1_0
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7 8 9
10 11 12
24 23 22 21 20 19