Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 5 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
Fig 2. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)
INTERRUPT
MASK
V
DD(IO)
P0_0 to P0_7
P1_0 to P1_7
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity
inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity
inversion
register data
002aad566
FF
data from
shift register
FF
FF
FF
Q1
Q2
V
SS
to INT
BUS-HOLD
AND
PULL-UP/PULL-DOWN
CONTROL
ESD
protection
diode
100 kΩ
V
DD(IO)