Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 29 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
14. Test information
Fig 23. Reset timing
SDA
SCL
002aad574
t
rst(GPIO)
50 %
30 %
50 % 50 %
50 %
t
rec(rst)
t
w(rst)
RESET
P0_0 to P0_7
P1_0 to P1_7
output off
START
t
rst(SDA)
ACK or read cycle
30 %
R
L
= load resistance.
C
L
= load capacitance includes jig and probe capacitance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generators.
(1) For SDA, no 500  pull-down.
Fig 24. Test circuitry for switching times
PULSE
GENERATOR
V
O
C
L
50 pF
R
L
500 Ω
002aad582
R
T
V
I
V
DD
DUT
2V
DD
open
V
SS
500 Ω
(1)