Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 28 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
[1] t
VD;ACK
= time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
[3] C
b
= total capacitance of one bus line in pF.
Port timing
t
v(Q)
data output valid time V
DD(IO)0
, V
DD(IO)1
=
V
DD
=1.1V
- 350 - 350 ns
V
DD(IO)0
, V
DD(IO)1
=
V
DD
= 2.3 V to 3.6 V
- 300 - 300 ns
t
su(D)
data input set-up time 150 - 150 - ns
t
h(D)
data input hold time 1 - 1 - s
Interrupt timing
t
v(INT)
valid time on pin INT -4 - 4s
t
rst(INT)
reset time on pin INT -4 - 4s
Reset
t
w(rst)
reset pulse width V
DD(IO)0
, V
DD(IO)1
=
V
DD
=1.1V
8- 8 -ns
V
DD(IO)0
, V
DD(IO)1
=
V
DD
= 2.3 V to 3.6 V
4- 4 -ns
t
rec(rst)
reset recovery time 0 - 0 - ns
t
rst(SDA)
SDA reset time Figure 23 - 400 - 400 ns
t
rst(GPIO)
GPIO reset time Figure 23 - 400 - 400 ns
Table 23. Dynamic characteristics
…continued
V
DD
= 1.1 V to 3.6 V; V
DD(IO)0
= 1.1 V to 3.6 V; V
DD(IO)1
= 1.1 V to 3.6 V; V
SS
=0V; T
amb
=  40  C to +85  C; unless
otherwise specified.
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Unit
Min Max Min Max
Fig 22. Definition of timing
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