Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 27 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
13. Dynamic characteristics
a. V
DD(IO)0
or V
DD(IO)1
=1.8V b. V
DD(IO)0
or V
DD(IO)1
=2.6V
Fig 21. I
OH
versus V
OH
8
16
24
I
OH
(mA)
0
V
DD
− V
OH
(V)
0 0.80.60.2 0.4
002aaf071
T
amb
= −40 °C
+25 °C
+85 °C
0
30
20
10
40
I
OL
(mA)
V
DD
− V
OH
(V)
0 0.80.60.2 0.4
002aaf072
T
amb
= −40 °C
+25 °C
+85 °C
Table 23. Dynamic characteristics
V
DD
= 1.1 V to 3.6 V; V
DD(IO)0
= 1.1 V to 3.6 V; V
DD(IO)1
= 1.1 V to 3.6 V; V
SS
=0V; T
amb
=  40  C to +85  C; unless
otherwise specified.
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Unit
Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
BUF
bus free time between a STOP and
START condition
4.7 - 1.3 - s
t
HD;STA
hold time (repeated) START
condition
4.0 - 0.6 - s
t
SU;STA
set-up time for a repeated START
condition
4.7 - 0.6 - s
t
SU;STO
set-up time for STOP condition 4.0 - 0.6 - s
t
VD;ACK
data valid acknowledge time
[1]
0.3 3.45 0.1 0.9 s
t
HD;DAT
data hold time 0 - 0 - ns
t
VD;DAT
data valid time
[2]
300 - 50 - ns
t
SU;DAT
data set-up time 250 - 100 - ns
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - s
t
HIGH
HIGH period of the SCL clock 4.0 - 0.6 - s
t
f
fall time of both SDA and SCL
signals
- 300 20 + 0.1C
b
[3]
300 ns
t
r
rise time of both SDA and SCL
signals
- 1000 20 + 0.1C
b
[3]
300 ns
t
SP
pulse width of spikes that must be
suppressed by the input filter
-50 - 50ns