Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 23 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
(1) Slave address shown in this example is for the 24-pin version.
Fig 15. Read from register
1000000AS0
START condition R/W
acknowledge
from slave
002aad571
A
acknowledge
from slave
SDA
A P
command byte
acknowledge
from master
data from register
DATA (first byte)
slave address
(1)
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
1000001A0
R/W
acknowledge
from slave
slave address
(1)
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
data from register
DATA (last byte)
This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition.
(1) Slave address shown in this example is for the 24-pin version.
Fig 16. Read Input port register
1000001AS0
slave address
(1)
START condition R/W acknowledge
from slave
002aad572
data from port
A
acknowledge
from master
SDA 1
no acknowledge
from master
read from
port
data into
port
data from port
DATA 1
DATA 4
INT
DATA 4
DATA 2
DATA 3
P
STOP
condition
t
v(INT)
t
rst(INT)
t
h(D)
t
su(D)
12345678SCL 9