Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 22 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
9. Bus transactions
Data is transmitted to the PCA9575 registers using ‘Write Byte’ transfers (see Figure 13
and Figure 14
).
Data is read from the PCA9575 registers using ‘Read Byte’ transfers (see Figure 15
and
Figure 16
).
(1) Slave address shown in this example is for the 24-pin version.
Fig 13. Write to Output port register
0 AS
slave address
(1)
START condition R/W acknowledge
from slave
002aad569
00010100
command byte
A
acknowledge
from slave
12345678SCL 9
SDA
DATA 1 A
write to port
data out from port
t
v(Q)
acknowledge
from slave
DATA 1 VALID
data to port
1000000
P
STOP
condition
(1) Slave address shown in this example is for the 24-pin version.
Fig 14. Write to Polarity inversion, Bus-hold enable, Pull-up/pull-down select, Configuration, Interrupt mask and
Interrupt status registers
0 AS
slave address
(1)
START condition R/W acknowledge
from slave
002aad570
000XXXX0
command byte
A
acknowledge
from slave
12345678SCL 9
SDA
DATA A
data to register
acknowledge
from slave
data to register
1000000
P
STOP
condition