Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 21 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of 8 bits is followed by one acknowledge
bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the
master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 11. System configuration
DDD
0$67(5
75$160,77(5
5(&(,9(5
6/$9(
5(&(,9(5
6/$9(
75$160,77(5
5(&(,9(5
0$67(5
75$160,77(5
0$67(5
75$160,77(5
5(&(,9(5
6'$
6&/
,

&%86
08/7,3/(;(5
6/$9(
Fig 12. Acknowledgement on the I
2
C-bus
DDD
6
67$57
FRQGLWLRQ

FORFNSXOVHIRU
DFNQRZOHGJHPHQW
QRWDFNQRZOHGJH
DFNQRZOHGJH
GDWDRXWSXW
E\WUDQVPLWWHU
GDWDRXWSXW
E\UHFHLYHU
6&/IURPPDVWHU