Datasheet
PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 18 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
7.6.15 Register 14 - Interrupt status port 0 register
This register is read-only. It is used to identify the source of interrupt.
Remark: If the interrupts are masked, this register returns all zeros.
7.6.16 Register 15 - Interrupt status port 1 register
This register is read-only. It is used to identify the source of interrupt.
Remark: If the interrupts are masked, this register returns all zeros.
7.7 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the PCA9575 in
a reset condition until V
DD
has reached V
POR
. At that point, the reset condition is released
and the PCA9575 registers and state machine initialize to their default states. The
power-on reset typically completes the reset and enables the part by the time the power
supply is above V
POR
. However, when it is required to reset the part by lowering the power
supply, it is necessary to lower it below 0.2 V.
7.8 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of t
w(rst)
. The
PCA9575 registers and I
2
C-bus state machine are held in their default state until the
RESET
input is once again HIGH.
Table 19. Register 14 - Interrupt status port 0 register (address 0Eh) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 S0.7 read only 0* identifies source of interrupt
6 S0.6 read only 0*
5 S0.5 read only 0*
4 S0.4 read only 0*
3 S0.3 read only 0*
2 S0.2 read only 0*
1 S0.1 read only 0*
0 S0.0 read only 0*
Table 20. Register 15 - Interrupt status port 1 register (address 0Fh) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 S1.7 read only 0* identifies source of interrupt
6 S1.6 read only 0*
5 S1.5 read only 0*
4 S1.4 read only 0*
3 S1.3 read only 0*
2 S1.2 read only 0*
1 S1.1 read only 0*
0 S1.0 read only 0*