Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 17 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
7.6.13 Register 12 - Interrupt mask port 0 register
All the bits of Interrupt mask port 0 register are set to logic 1 upon power-on or software
reset, thus disabling interrupts. Interrupts may be enabled by setting corresponding mask
bits to logic 0.
7.6.14 Register 13 - Interrupt mask port 1 register
All the bits of Interrupt mask port 1 register are set to logic 1 upon power-on or software
reset, thus disabling interrupts. Interrupts may be enabled by setting corresponding mask
bits to logic 0.
Table 17. Register 12 - Interrupt mask port 0 register (address 0Ch) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 M0.7 R/W 1* enable or disable interrupts
0 = enable interrupt
1 = disable interrupt (default value)
6M0.6 R/W 1*
5M0.5 R/W 1*
4M0.4 R/W 1*
3M0.3 R/W 1*
2M0.2 R/W 1*
1M0.1 R/W 1*
0M0.0 R/W 1*
Table 18. Register 13 - Interrupt mask port 1 register (address 0Dh) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 M1.7 R/W 1* enable or disable interrupts
0 = enable interrupt
1 = disable interrupt (default value)
6M1.6 R/W 1*
5M1.5 R/W 1*
4M1.4 R/W 1*
3M1.3 R/W 1*
2M1.2 R/W 1*
1M1.1 R/W 1*
0M1.0 R/W 1*