Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 16 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
7.6.11 Register 10 - Output port 0 register
This register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by Register 8. Bit values in this register have no effect on pins defined as
inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the
output selection, not the actual pin value.
7.6.12 Register 11 - Output port 1 register
This register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by Register 9. Bit values in this register have no effect on pins defined as
inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the
output selection, not the actual pin value.
Table 15. Register 10 - Output port 0 register (address 0Ah) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 O0.7 R/W 0* reflects outgoing logic levels of pins defined as
outputs by Register 8
6O0.6 R/W 0*
5O0.5 R/W 0*
4O0.4 R/W 0*
3O0.3 R/W 0*
2O0.2 R/W 0*
1O0.1 R/W 0*
0O0.0 R/W 0*
Table 16. Register 11 - Output port 1 register (address 0Bh) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 O1.7 R/W 0* reflects outgoing logic levels of pins defined as
outputs by Register 9
6O1.6 R/W 0*
5O1.5 R/W 0*
4O1.4 R/W 0*
3O1.3 R/W 0*
2O1.2 R/W 0*
1O1.1 R/W 0*
0O1.0 R/W 0*