Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 15 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
7.6.9 Register 8 - Configuration port 0 register
This register configures the direction of the I/O pins. If a bit in this register is set (written
with logic 1), the corresponding port 0 pin is enabled as an input with high-impedance
output driver. If a bit in this register is cleared (written with logic 0), the corresponding
port 0 pin is enabled as an output. At reset, the device ports are inputs.
7.6.10 Register 9 - Configuration port 1 register
This register configures the direction of the I/O pins. If a bit in this register is set (written
with logic 1), the corresponding port 1 pin is enabled as an input with high-impedance
output driver. If a bit in this register is cleared (written with logic 0), the corresponding
port 1 pin is enabled as an output. At reset, the device ports are inputs.
Table 13. Register 8 - Configuration port 0 register (address 08h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 C0.7 R/W 1* configures the direction of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value)
6C0.6 R/W 1*
5C0.5 R/W 1*
4C0.4 R/W 1*
3C0.3 R/W 1*
2C0.2 R/W 1*
1C0.1 R/W 1*
0C0.0 R/W 1*
Table 14. Register 9 - Configuration port 1 register (address 09h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 C1.7 R/W 1* configures the direction of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value)
6C1.6 R/W 1*
5C1.5 R/W 1*
4C1.4 R/W 1*
3C1.3 R/W 1*
2C1.2 R/W 1*
1C1.1 R/W 1*
0C1.0 R/W 1*