Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 13 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
7.6.6 Register 5 - Bus-hold/pull-up/pull-down enable 1 register
Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins.
Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank 1. In this mode, the
pull-up/pull-downs are disabled for I/O bank 1. Setting the bit 0 to logic 0 disables
bus-hold feature.
Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.
Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 7. Setting
the bit 1 to logic 0 disables pull-up/pull-downs on the I/O bank 1 pins and contents of
Register 7 have no effect on the I/O.
Table 10. Register 5 - Bus-hold/pull-up/pull-down enable 1 register (address 05h)
bit description
Legend: * default value.
Bit Symbol Access Value Description
7 E1.7 R/W X not used
6E1.6 R/W X
5E1.5 R/W X
4E1.4 R/W X
3E1.3 R/W X
2E1.2 R/W X
1 E1.1 R/W 0* allows the user to enable/disable pull-up/pull-downs on the
I/O bank 1 pins
0 = disables pull-up/pull-downs on the I/O bank 1 pins and
contents of Register 7 have no effect on the I/O bank 0
(default value)
1 = enables selection of pull-up/pull-down using Register 7
0 E1.0 R/W 0* allows user to enable/disable the bus-hold feature for the
I/O bank 1 pins
0 = disables bus-hold feature (default value)
1 = enables bus-hold feature