Datasheet

PCA9575 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 20 May 2014 11 of 42
NXP Semiconductors
PCA9575
16-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
7.6.2 Register 1 - Input port 1 register
This register is read-only. It reflects the incoming logic levels of the pins, regardless of
whether the pin is defined as an input or an output by the Configuration register. Writes to
this register are acknowledged but have no effect.
The default ‘X’ is determined by the externally applied logic level.
7.6.3 Register 2 - Polarity inversion port 0 register
This register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 6. Register 1 - Input port 1 register (address 01h) bit description
Bit Symbol Access Value Description
7 IO1.7 read only X determined by externally applied logic level
6 IO1.6 read only X
5 IO1.5 read only X
4 IO1.4 read only X
3 IO1.3 read only X
2 IO1.2 read only X
1 IO1.1 read only X
0 IO1.0 read only X
Table 7. Register 2 - Polarity Inversion port 0 register (address 02h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 N0.7 R/W 0* inverts polarity of Input port 0 register data
0 = Input port 0 register data retained (default value)
1 = Input port 0 register data inverted
6N0.6 R/W 0*
5N0.5 R/W 0*
4N0.4 R/W 0*
3N0.3 R/W 0*
2N0.2 R/W 0*
1N0.1 R/W 0*
0N0.0 R/W 0*