Datasheet

Product data sheet Rev. 4 — 20 May 2014 10 of 42

NXP Semiconductors

PCA9575

16-bit I

C-bus and SMBus, level translating, low voltage GPIO

7.5 Writing to port registers

Data is transmitted to the PCA9575 by sending the device address and setting the least

significant bit to logic 0 (see Figure 6

or Figure 7 for device address). The command byte

is sent after the address and determines which register receives the data following the

command byte. Each 8-bit register may be updated independently of the other registers.

7.6 Reading the port registers

In order to read data from the PCA9575, the bus master must first send the PCA9575

address with the least significant bit set to a logic 0 (see Figure 6

or Figure 7 for device

address). The command byte is sent after the address and determines which register is

accessed. After a restart, the device address is sent again but this time, the least

significant bit is set to logic 1. Data from the register defined by the command byte will

then be sent by the PCA9575. Data is clocked into the register on the falling edge of the

acknowledge clock pulse. After the first byte is read, additional bytes may be read using

the auto-increment feature.

7.6.1 Register 0 - Input port 0 register

This register is read-only. It reflects the incoming logic levels of the pins, regardless of

whether the pin is defined as an input or an output by the Configuration register. Writes to

this register are acknowledged but have no effect.

The default ‘X’ is determined by the externally applied logic level.

0Dh 1101MSK1 read/writeInterrupt mask port1 register

0Eh 1110INTS0 read only Interrupt status port0 register

0Fh 1111INTS1 read only Interrupt status port1 register

Table 4. Register summary

…continued

Table 5. Register 0 - Input port 0 register (address 00h) bit description

Bit Symbol Access Value Description

7 IO0.7 read only X determined by externally applied logic level

6 IO0.6 read only X

5 IO0.5 read only X

4 IO0.4 read only X

3 IO0.3 read only X

2 IO0.2 read only X

1 IO0.1 read only X

0 IO0.0 read only X