Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 Device address
- 7.2 Command register
- 7.3 Register definitions
- 7.4 Writing to port registers
- 7.5 Reading the port registers
- 7.5.1 Register 0 - Input port register
- 7.5.2 Register 1 - Polarity inversion register
- 7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register
- 7.5.4 Register 3 - Pull-up/pull-down selector register
- 7.5.5 Register 4 - Configuration register
- 7.5.6 Register 5 - Output port register
- 7.5.7 Register 6 - Interrupt mask register
- 7.5.8 Register 7 - Interrupt status register
- 7.6 Power-on reset
- 7.7 RESET input
- 7.8 Software reset
- 7.9 Interrupt output (INT)
- 7.10 Standby
- 8. Characteristics of the I2C-bus
- 9. Bus transactions
- 10. Application design-in information
- 11. Limiting values
- 12. Static characteristics
- 13. Dynamic characteristics
- 14. Test information
- 15. Package outline
- 16. Handling information
- 17. Soldering of SMD packages
- 18. Abbreviations
- 19. Revision history
- 20. Legal information
- 21. Contact information
- 22. Contents
PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 25 September 2014 9 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register
Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins.
Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank. In this mode, the
pull-up/pull-downs will be disabled. Setting the bit 0 to logic 0 disables bus-hold feature.
Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.
Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 3. Setting
the bit 1 to logic 0 disables pull-up/pull-downs on the I/O pins and contents of Register 3
will have no effect on the I/O.
Table 7. Register 2 - Bus-hold/pull-up/pull-down enable register (address 02h) bit
description
Legend: * default value.
Bit Symbol Access Value Description
7 E0.7 R/W X not used
6E0.6 R/W X
5E0.5 R/W X
4E0.4 R/W X
3E0.3 R/W X
2E0.2 R/W X
1 E0.1 R/W 0* allows the user to enable/disable pull-up/pull-downs on the
I/O pins
0 = disables pull-up/pull-downs on the I/O pins and
contents of Register 3 will have no effect on the I/O
(default value)
1 = enables selection of pull-up/pull-down using
Register 3
0 E0.0 R/W 0* allows user to enable/disable the bus-hold feature for the I/O
pins
0 = disables bus-hold feature (default value)
1 = enables bus-hold feature